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1. 发明申请

US20110317505A1 INTERNAL BYPASSING OF MEMORY ARRAY DEVICES 有权
标题翻译：内存阵列设备的内部旁路
公开(公告)号：US20110317505A1
公开(公告)日：2011-12-29
申请号：US12822058
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G11C7/00
CPC分类号： G11C16/02 , G11C7/1048 , G11C11/413 , G11C2207/002
摘要： An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.
摘要翻译：用于存储器阵列的输出控制电路包括在读取和写入操作之前预先充电到第一逻辑状态的锁存输出节点; 在读取操作期间将存储器单元数据从存储器读取路径耦合到输出节点的第一逻辑，由定时信号控制的第一逻辑; 第二逻辑，其在写入操作期间通过将其与输出节点分离而在内部旁路存储器读取路径，使得写入存储器阵列的写入数据的逻辑导数也耦合到输出节点，第二逻辑也由定时控制信号; 并且其中，所述输出节点在所述写入操作期间从所述第一逻辑状态到第二逻辑状态的转变在与所述读取操作期间相同转换的时间范围内发生。

2. 发明申请

US20110320851A1 PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT 有权
标题翻译：端口使能信号生成用于获取存储器阵列设备输出
公开(公告)号：US20110320851A1
公开(公告)日：2011-12-29
申请号：US12822021
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G06F1/10 , G11C11/419
摘要： A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.
摘要翻译：产生用于将存储器阵列数据门控到输出节点的动态端口使能信号的方法包括产生输入动态时钟信号的可编程前沿时钟信号导出; 产生所述输入动态时钟信号的可编程后沿时钟信号导出，其中所述前沿时钟信号导出和所述后沿时钟信号导出可相对于彼此独立地可编程; 以及利用静态输入使能信号选通产生的可编程前导和后沿时钟信号导出，以便产生端口使能信号，使得当非活动时，端口使能信号防止早期存储器阵列数据耦合到输出节点。

3. 发明申请

US20110317496A1 JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA 失效
标题翻译：用于锁定内存阵列输出数据的JAM LATCH
公开(公告)号：US20110317496A1
公开(公告)日：2011-12-29
申请号：US12822038
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/413
摘要： A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.
摘要翻译：用于数据节点的卡锁装置包括：前馈反相器，其具有耦合到数据节点的输入; 反馈逆变器，其具有连接到所述前馈逆变器的输出的输入端，所述反馈反相器的输出连接到所述数据节点; 隔离装置，其将反馈反相器与电源轨选择性地分离，该隔离装置由复位装置的时钟信号控制，该复位装置将数据节点复位到第一逻辑状态，使得反馈反相器与电源轨的解耦一致将数据节点重置为第一逻辑状态; 以及选择性地增加反馈逆变器的下拉强度的余量测试装置。

4. 发明申请

US20110317499A1 SPLIT VOLTAGE LEVEL RESTORE AND EVALUATE CLOCK SIGNALS FOR MEMORY ADDRESS DECODING 有权
标题翻译：分离电压电平恢复和评估用于存储器地址解码的时钟信号
公开(公告)号：US20110317499A1
公开(公告)日：2011-12-29
申请号：US12821824
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G11C7/00 , G11C8/10
CPC分类号： G11C7/22 , G11C7/222 , G11C8/10
摘要： A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level.
摘要翻译：实现存储器件的电压电平移位的方法包括将一个或多个评估时钟信号耦合到存储器地址解码电路，所述一个或多个评估时钟信号以第一电压供应电平工作; 以及将恢复时钟信号耦合到存储器地址解码电路，所述还原时钟信号在高于所述第一电压供应电平的第二电压供应电平下工作; 其中存储器地址解码电路的一个或多个输出在第二电压供应电平下工作。

5. 发明授权

US08351278B2 Jam latch for latching memory array output data 失效
标题翻译：用于锁存存储器阵列输出数据的卡锁
公开(公告)号：US08351278B2
公开(公告)日：2013-01-08
申请号：US12822038
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/413
摘要： A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.
摘要翻译：用于数据节点的卡锁装置包括：前馈反相器，其具有耦合到数据节点的输入; 反馈逆变器，其具有连接到所述前馈逆变器的输出的输入端，所述反馈反相器的输出连接到所述数据节点; 隔离装置，其将反馈反相器与电源轨选择性地分离，该隔离装置由复位装置的时钟信号控制，该复位装置将数据节点复位到第一逻辑状态，使得反馈反相器与电源轨的解耦一致将数据节点重置为第一逻辑状态; 以及选择性地增加反馈逆变器的下拉强度的余量测试装置。

6. 发明授权

US08599642B2 Port enable signal generation for gating a memory array device output 有权
标题翻译：用于门控存储器阵列器件输出的端口使能信号生成
公开(公告)号：US08599642B2
公开(公告)日：2013-12-03
申请号：US12822021
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C8/18 , G06F1/04
CPC分类号： G06F1/10 , G11C11/419
摘要： A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.
摘要翻译：产生用于将存储器阵列数据门控到输出节点的动态端口使能信号的方法包括产生输入动态时钟信号的可编程前沿时钟信号导出; 产生所述输入动态时钟信号的可编程后沿时钟信号导出，其中所述前沿时钟信号导出和所述后沿时钟信号导出可相对于彼此独立地可编程; 以及利用静态输入使能信号选通产生的可编程前导和后沿时钟信号导出，以便产生端口使能信号，使得当非活动时，端口使能信号防止早期存储器阵列数据耦合到输出节点。

7. 发明授权

US08345497B2 Internal bypassing of memory array devices 有权
标题翻译：内存阵列设备的内部旁路
公开(公告)号：US08345497B2
公开(公告)日：2013-01-01
申请号：US12822058
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C7/00
CPC分类号： G11C16/02 , G11C7/1048 , G11C11/413 , G11C2207/002
摘要： An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.
摘要翻译：用于存储器阵列的输出控制电路包括在读取和写入操作之前预先充电到第一逻辑状态的锁存输出节点; 在读取操作期间将存储器单元数据从存储器读取路径耦合到输出节点的第一逻辑，由定时信号控制的第一逻辑; 第二逻辑，其在写入操作期间通过将其与输出节点分离而在内部旁路存储器读取路径，使得写入存储器阵列的写入数据的逻辑导数也耦合到输出节点，第二逻辑也由定时控制信号; 并且其中，所述输出节点在所述写入操作期间从所述第一逻辑状态到第二逻辑状态的转变在与所述读取操作期间相同转换的时间范围内发生。

8. 发明授权

US08345490B2 Split voltage level restore and evaluate clock signals for memory address decoding 有权
标题翻译：分离电压电平恢复和评估用于存储器地址解码的时钟信号
公开(公告)号：US08345490B2
公开(公告)日：2013-01-01
申请号：US12821824
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C8/10
摘要： A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level.
摘要翻译：实现存储器件的电压电平移位的方法包括将一个或多个评估时钟信号耦合到存储器地址解码电路，所述一个或多个评估时钟信号以第一电压供应电平工作; 以及将恢复时钟信号耦合到存储器地址解码电路，所述还原时钟信号在高于所述第一电压供应电平的第二电压供应电平下工作; 其中存储器地址解码电路的一个或多个输出在第二电压供应电平下工作。

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