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21. 发明授权

US07253015B2 Low doped layer for nitride-based semiconductor device 失效
标题翻译：用于氮化物基半导体器件的低掺杂层
公开(公告)号：US07253015B2
公开(公告)日：2007-08-07
申请号：US10780526
申请日：2004-02-17
申请人： Milan Pophristic , Michael Murphy , Richard A. Stall , Bryan S. Shelton , Linlin Liu , Alex D. Ceruzzi
发明人： Milan Pophristic , Michael Murphy , Richard A. Stall , Bryan S. Shelton , Linlin Liu , Alex D. Ceruzzi
IPC分类号： H01L21/00 , H01L33/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/452 , H01L29/157 , H01L29/2003 , H01L29/475 , H01L29/7787 , H01L29/872
摘要： A repeatable and uniform low doped layer is formed using modulation doping by forming alternating sub-layers of doped and undoped nitride semiconductor material atop another layer. A Schottky diode is formed of such a low doped nitride semiconductor layer disposed atop a much more highly doped nitride semiconductor layer. The resulting device has both a low on-resistance when the device is forward biased and a high breakdown voltage when the device is reverse biased.
摘要翻译：通过在另一层上形成掺杂和未掺杂的氮化物半导体材料的交替子层，通过调制掺杂形成可重复且均匀的低掺杂层。肖特基二极管由设置在更高掺杂的氮化物半导体层顶上的这种低掺杂氮化物半导体层形成。当器件正向偏置时，所得器件具有低导通电阻，器件反向偏置时具有高击穿电压。

22. 发明授权

US07084475B2 Lateral conduction Schottky diode with plural mesas 有权
标题翻译：具有多个台面的横向导通肖特基二极管
公开(公告)号：US07084475B2
公开(公告)日：2006-08-01
申请号：US10780363
申请日：2004-02-17
申请人： Bryan S. Shelton , Linlin Liu , Alex D. Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard A. Stall , Xiang Gao , Ivan Eliashevich
发明人： Bryan S. Shelton , Linlin Liu , Alex D. Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard A. Stall , Xiang Gao , Ivan Eliashevich
IPC分类号： H01L29/47
CPC分类号： H01L24/81 , H01L29/0692 , H01L29/2003 , H01L29/872 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01023 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/12032 , H01L2924/00
摘要： A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.
摘要翻译：横向导通肖特基二极管包括形成肖特基接触的多个台面区域，其至少由欧姆接触分开，以减小电流路径长度并减少肖特基接触中的电流拥挤，从而降低器件的正向电阻。多个台面可以彼此隔离并且具有优化的尺寸和形状以减少前向阻力。或者，一些台面可以是手指形状并与中央台面或桥台面相交，并且部分或全部欧姆接触件与指状台面相互交错。指状台面的尺寸和相交结构的周长可以被优化以减小正向阻力。肖特基二极管可以以倒装芯片布置的方式安装到基座上，这进一步降低了正向电压，并且改善了功率论文并减少了发热。

23. 发明申请

US20050179104A1 Lateral conduction schottky diode with plural mesas 有权
标题翻译：具有多个台面的横向导通肖特基二极管
公开(公告)号：US20050179104A1
公开(公告)日：2005-08-18
申请号：US10780363
申请日：2004-02-17
申请人： Bryan Shelton , Linlin Liu , Alex Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard Stall , Xiang Gao , Ivan Eliashevich
发明人： Bryan Shelton , Linlin Liu , Alex Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard Stall , Xiang Gao , Ivan Eliashevich
IPC分类号： H01L21/60 , H01L29/06 , H01L29/20 , H01L29/47 , H01L29/872 , H01L21/00 , H01L31/0328
CPC分类号： H01L24/81 , H01L29/0692 , H01L29/2003 , H01L29/872 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01023 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/12032 , H01L2924/00
摘要： A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.
摘要翻译：横向导通肖特基二极管包括形成肖特基接触的多个台面区域，其至少由欧姆接触分开，以减小电流路径长度并减少肖特基接触中的电流拥挤，从而降低器件的正向电阻。多个台面可以彼此隔离并且具有优化的尺寸和形状以减少前向阻力。或者，一些台面可以是手指形状并与中央台面或桥台面相交，并且部分或全部欧姆接触件与指状台面相互交错。指状台面的尺寸和相交结构的周长可以被优化以减小正向阻力。肖特基二极管可以以倒装芯片布置的方式安装到基座上，这进一步降低了正向电压，并且改善了功率论文并减少了发热。

24. 发明授权

US08022495B2 PIN diode structure with zinc diffusion region 失效
标题翻译： PIN二极管结构与锌扩散区
公开(公告)号：US08022495B2
公开(公告)日：2011-09-20
申请号：US12420213
申请日：2009-04-08
申请人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
发明人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
IPC分类号： H01L31/06
CPC分类号： H01L31/105
摘要： A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, and a first type window layer disposed over the intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer is disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.
摘要翻译： PIN光电二极管，其具有基板，设置在基板上的第一类型电极层，设置在第一类型电极层的一部分上的第一本征材料层，以及设置在本征层上的第一类型窗口层。本征材料的岛状区域设置在窗口层上方，并且电介质层设置在岛状区域和至少所述岛状区域的周边部分上，从而在岛状区域中形成开口。掺杂剂通过开口扩散，以便形成延伸到本征材料的第一层中的PN结。

25. 发明授权

US07863172B2 Gallium nitride semiconductor device 有权
标题翻译：氮化镓半导体器件
公开(公告)号：US07863172B2
公开(公告)日：2011-01-04
申请号：US12249099
申请日：2008-10-10
申请人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
发明人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
IPC分类号： H01L29/872 , H01L29/47
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/475
摘要： A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
摘要翻译：由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层，其厚度介于1微米与6微米之间，设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。优化了层厚度和细长指状物的长度和宽度，以实现具有大于500伏特的击穿电压，超过1安培的电流容量和小于3伏特的正向电压的器件。

26. 发明授权

US07518240B2 Deposition pattern for eliminating backside metal peeling during die separation in semiconductor device fabrication 有权
标题翻译：用于消除半导体器件制造中的芯片分离期间的背面金属剥离的沉积图案
公开(公告)号：US07518240B2
公开(公告)日：2009-04-14
申请号：US11728751
申请日：2007-03-27
申请人： Douglas Collins , Linlin Liu , Elaine Taylor
发明人： Douglas Collins , Linlin Liu , Elaine Taylor
IPC分类号： H01L23/48
CPC分类号： H01L21/6836 , H01L21/78 , H01L23/562 , H01L2221/68327 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer that includes a plurality of groups of active devices or circuits on a first side of the wafer and a patterned electrical contact on the backside of the wafer. Each group consisting of an active device or circuit is intended to be diced into a discrete chip. The backside of the wafer includes a metal layer patterned into discrete spaced-apart deposits that form an electrical contact to the semiconductor and the respective group of active devices. The deposits are not contiguously or laterally connected to each other and function to protect the metal layer from peeling or detaching from the wafer during dicing of the semiconductor wafer into chips.
摘要翻译：一种半导体晶片，其在晶片的第一侧上包括多组有源器件或电路，并且在晶片的背面具有图案化的电接触。由有源器件或电路组成的每个组件都将被切割成分立的芯片。晶片的背面包括图案化成离散间隔开的沉积物的金属层，其形成与半导体和相应组的有源器件的电接触。沉积物彼此不连续或横向连接，并且用于在将半导体晶片切割成芯片期间保护金属层免受剥离或从晶片分离。

27. 发明授权

US07439599B2 PIN photodiode structure and fabrication process for reducing dielectric delamination 有权
标题翻译： PIN光电二极管结构和减少介电分层的制造工艺
公开(公告)号：US07439599B2
公开(公告)日：2008-10-21
申请号：US11079708
申请日：2005-03-14
申请人： Xiang Gao , Alex Ceruzzi , Steve Schwed , Linlin Liu , Mark Gottfried
发明人： Xiang Gao , Alex Ceruzzi , Steve Schwed , Linlin Liu , Mark Gottfried
IPC分类号： H01L31/00
CPC分类号： H01L31/02161 , H01L31/105
摘要： A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.
摘要翻译： PIN光电二极管，以及制造PIN光电二极管的方法，该光电二极管减少了介质分层并提高了器件的可靠性该工艺通过在衬底上形成第一类型电极层而进行; 形成第一类型电极层的本征层; 在本征层上形成第二类型的电极层; 蚀刻第二类型电极层以限定台面形结构; 以及在所述台面形结构上沉积钝化材料。

28. 发明申请

US20060151868A1 Package for gallium nitride semiconductor devices 审中-公开
标题翻译：氮化镓半导体器件封装
公开(公告)号：US20060151868A1
公开(公告)日：2006-07-13
申请号：US11032666
申请日：2005-01-10
申请人： TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Boris Peres , Alex Ceruzzi
发明人： TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Boris Peres , Alex Ceruzzi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3107 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/49171 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/20755 , H01L2924/2076 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/43 , H01L2924/01006
摘要： A packaged semiconductor device, in particular a gallium nitride semiconductor structure including a lower semiconductor layer and an upper semiconductor layer disposed over a portion of the lower semiconductor layer. The semiconductor structure includes a plurality of mesas projecting upwardly from the lower layer, each of the mesas including a portion of the upper layer and defining an upper contact surface separated form adjacent mesas by a portion of the lower layer surface. The device further includes a die mounting support, wherein the bottom surface of the die is attached to the top surface of the die mounting support; and a plurality of spaced external conductors extending from the support, at least once of said spaced external conductors having a bond wire post at one end thereof; with a bonding wire extending between the bond wire post and a contact region to the top surface of the plurality of mesas.
摘要翻译：封装的半导体器件，特别是包括下半导体层和设置在下半导体层的一部分上的上半导体层的氮化镓半导体结构。半导体结构包括从下层向上突出的多个台面，每个台面包括上层的一部分，并且限定由下层表面的一部分与相邻台面分开的上接触表面。该装置还包括模具安装支撑件，其中模具的底表面附接到模具安装支撑件的顶表面; 以及从所述支撑件延伸的多个间隔开的外部导体，所述间隔开的外部导体中的至少一个在其一端具有接合线柱; 其中接合线在接合线柱和与多个台面的顶表面之间的接触区域之间延伸。

29. 发明申请

US20060060933A1 PIN diode structure with zinc diffusion region 失效
公开(公告)号：US20060060933A1
公开(公告)日：2006-03-23
申请号：US11230959
申请日：2005-09-19
申请人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
发明人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
IPC分类号： H01L31/105
CPC分类号： H01L31/105
摘要： A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, a first type window layer disposed over said intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.

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