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21. 发明授权

US06510508B1 Translation lookaside buffer flush filter 有权
标题翻译：翻译后备缓冲器冲洗过滤器
公开(公告)号：US06510508B1
公开(公告)日：2003-01-21
申请号：US09595597
申请日：2000-06-15
申请人： Gerald D. Zuraski, Jr. , Michael T. Clark
发明人： Gerald D. Zuraski, Jr. , Michael T. Clark
IPC分类号： G06F1212
CPC分类号： G06F12/1027 , G06F2212/682 , G06F2212/683
摘要： A translation lookaside buffer (TLB) flush filter. In one embodiment, a central processing unit includes a TLB for storing recent address translations. A TLB flush filter monitors blocks of memory from which address translations have been loaded and cached in the TLB. The TLB flush filter is configured to detect if any of the underlying address translations in memory have changed. If no changes have occurred, the TLB flush filter may then prevent a flush of the TLB following the next context switch. If changes have occurred to the underlying address translations, the TLB flush filter may then allow a flush of the TLB following a context switch.
摘要翻译：翻译后备缓冲器（TLB）冲洗过滤器。在一个实施例中，中央处理单元包括用于存储最近地址转换的TLB。 TLB刷新过滤器监视在TLB中加载并缓存地址转换的内存块。 TLB刷新过滤器被配置为检测内存中的任何底层地址转换是否已更改。如果没有发生更改，则TLB刷新过滤器可能阻止在下一个上下文切换之后刷新TLB。如果底层地址转换发生更改，则TLB刷新过滤器可以允许在上下文切换之后刷新TLB。

22. 发明授权

US06493819B1 Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor 有权
标题翻译：在更新微处理器中寄存器的一部分时，合并窄寄存器以分辨数据依赖性
公开(公告)号：US06493819B1
公开(公告)日：2002-12-10
申请号：US09442209
申请日：1999-11-16
申请人： Eric W. Mahurin , Scott A. White , Michael T. Clark
发明人： Eric W. Mahurin , Scott A. White , Michael T. Clark
IPC分类号： G06F930
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A microprocessor includes general purpose registers which may be accessed or updated in portions. Dependencies may be created between an instruction which updates only a portion of a destination register and a subsequent instruction which requires a larger portion of that destination register, inclusive of the smaller updated portion, as a source. To resolve such dependencies between instructions, a determination is made upon decode of an instruction whether it updates only a portion of a destination or the entire destination. If only a portion of the destination is updated by the instruction, a read of the destination is done prior to execution of the instruction and the data read from the destination is merged with the results of the instruction execution. The merged data is then conveyed as the results of the instruction execution.
摘要翻译：微处理器包括可以部分访问或更新的通用寄存器。可以在只更新目的地寄存器的一部分的指令和需要该目的地寄存器的较大部分（包括较小的更新部分）作为源的后续指令之间产生依赖性。为了解决指令之间的这种依赖性，在解码指令时是否仅更新目的地或整个目的地的一部分进行确定。如果只有目的地的一部分被指令更新，则在执行指令之前完成目的地的读取，并且从目的地读取的数据与指令执行的结果合并。然后将合并的数据作为指令执行的结果传送。

23. 发明授权

US06446189B1 Computer system including a novel address translation mechanism 有权
标题翻译：计算机系统包括一种新颖的地址转换机制
公开(公告)号：US06446189B1
公开(公告)日：2002-09-03
申请号：US09323321
申请日：1999-06-01
申请人： Gerald D. Zuraski, Jr. , Frederick D. Weber , William A. Hughes , William K. Lewchuk , Scott A. White , Michael T. Clark
发明人： Gerald D. Zuraski, Jr. , Frederick D. Weber , William A. Hughes , William K. Lewchuk , Scott A. White , Michael T. Clark
IPC分类号： G06F1200
CPC分类号： G06F12/1054
摘要： A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e.g., a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU. The BIU includes address translation circuitry, a multiplexer, and gating logic, and returns the physical address corresponding to the linear address to the cache unit. The cache unit stores the physical address and the linear address within the TLB. The processor may also include a programmable control register and a microexecution unit. Upon detecting a change in state of an external masking signal, the microexecution unit may flush the contents of the TLB and modify a masking bit within the control register to reflect a new state of the masking signal.
摘要翻译：呈现包括耦合到总线接口单元（BIU）的高速缓存单元的处理器。地址信号选择和屏蔽功能由BIU内的电路而不是在高速缓存单元内执行，而由BIU生成的物理地址存储在TLB内。结果，从高速缓存单元内的临界速度路径消除了地址信号选择和屏蔽电路（例如，多路复用器和门控逻辑），从而允许高速缓存单元的操作速度增加。高速缓存单元存储数据项，并产生与所接收的线性地址对应的数据项。缓存单元内的翻译后备缓冲器（TLB）存储多个线性地址和对应的物理地址。当在TLB内没有找到与接收到的线性地址对应的物理地址时，高速缓存单元将线性地址传递给BIU。 BIU包括地址转换电路，多路复用器和门控逻辑，并将对应于线性地址的物理地址返回到高速缓存单元。高速缓存单元存储TLB内的物理地址和线性地址。处理器还可以包括可编程控制寄存器和微执行单元。在检测到外部屏蔽信号的状态变化时，微执行单元可以刷新TLB的内容并修改控制寄存器内的屏蔽位以反映掩蔽信号的新状态。

24. 发明授权

US5626327A Solenoid-driven valve having a roller bearing 失效
标题翻译：电磁阀带有滚子轴承
公开(公告)号：US5626327A
公开(公告)日：1997-05-06
申请号：US430203
申请日：1995-04-27
申请人： Michael T. Clark
发明人： Michael T. Clark
IPC分类号： F02M25/07 , F16K31/06
CPC分类号： F02M26/67 , F02M26/53 , F02M26/74
摘要： An exhaust gas recirculation valve comprising a solenoid device and a valve mechanism is disclosed. The solenoid device has a coil, an armature, and a roller bearing to support a guide mechanically coupled to the armature. The armature and the guide translate with respect to the roller bearing in response to energizing the solenoid device by applying an electrical signal to the coil. The valve mechanism has a stem member which translates with the stem guide for varying fluidic communication between an inlet port and an outlet port in response to the electrical signal.
摘要翻译：公开了一种包括螺线管装置和阀机构的排气再循环阀。螺线管装置具有线圈，电枢和用于支撑机械地联接到电枢的引导件的滚子轴承。响应于通过向线圈施加电信号来激励螺线管装置，电枢和引导件相对于滚子轴承平移。阀机构具有杆构件，其与杆引导件平行，用于响应于电信号改变入口和出口之间的流体连通。

25. 发明授权

US5604214A Reduction of boar odor in meat 失效
标题翻译：减少肉中的野猪气味
公开(公告)号：US5604214A
公开(公告)日：1997-02-18
申请号：US513952
申请日：1995-10-20
申请人： Hector W. Alila , Michael T. Clark , Richard D. Hedde , Mark A. Levy , Thomas O. Lindsey
发明人： Hector W. Alila , Michael T. Clark , Richard D. Hedde , Mark A. Levy , Thomas O. Lindsey
IPC分类号： A61K31/56 , A23L1/31 , A61K31/33
CPC分类号： A61K31/56
摘要： This invention relates to a method for eliminating or lessening the incidence of boar odor in meat reared from male pigs which comprises administering to such male pigs an effective amount of a boar 4-ene-5-.alpha.-reductase inhibiting compound with or without further active ingredients. Also provided is a method for preventing the formation of 5-.alpha.-androst-16-en-3-one in male pigs which comprises administering to such male pigs a presently discovered boar 4-ene-5-.alpha.-reductase inhibiting compound.
摘要翻译： PCT No.PCT / US94 / 02600 Sec。 371 1995年10月20日第 102（e）日期1995年10月20日PCT 1994年3月10日PCT公布。出版物WO94 / 20112 PCT 日期1994年9月15日本发明涉及一种消除或减轻从雄性猪饲养的肉类中的野猪气味发生率的方法，其特征在于，对这些雄性猪施用有效量的公猪4-烯-5α-还原酶抑制化合物有或没有进一步的活性成分。还提供了一种用于防止在雄性猪中形成5-阿尔法 - 雄烯-16-烯-3-酮的方法，其包括向这些雄性猪施用目前发现的公猪4-烯-5-α-还原酶抑制化合物。

26. 发明授权

US4939132A Novel 5-alkylsulfonylsalicylanilides and microbiocidal compositions for controlling the growth of microorganisms 失效
标题翻译：用于控制微生物生长的新型5-烷基磺酰基水杨酰胺和杀微生物组合物
公开(公告)号：US4939132A
公开(公告)日：1990-07-03
申请号：US723080
申请日：1985-04-15
申请人： Robert A. Coburn , Richard T. Evans , Robert J. Genco , Michael T. Clark
发明人： Robert A. Coburn , Richard T. Evans , Robert J. Genco , Michael T. Clark
IPC分类号： A61K31/60 , A61K8/46 , A61K8/69 , A61K31/165 , A61K31/18 , A61P1/02 , A61P31/04 , A61Q11/00 , C07C67/00 , C07C233/12 , C07C233/65 , C07C313/00 , C07C317/46 , C07C323/65
CPC分类号： A61Q11/00 , A61K8/466 , A61K8/69
摘要： This invention relates to new 5-alkylsulfonylsalicylanilides and methods for their use. More particularly, the invention relates to compounds of the formula: ##STR1## Wherein Z is a substituted or unsubstituted phenyl ring of from 6 to 30 carbon atoms including substituents, R is a substituted or unsubstituted alkylsulfonyl group of from 1 to 20 carbon atoms including substitutents; and X is a radical selected from the group consisting of --CN, --NO.sub.2, --H, halogen, lower alkyl or lower haloalkyl.The above compounds and compositions containing them are effective antiseptics against a wide range of microorganisms, especially bacteria, and are surprisingly highly effective against microorganisms, particularly S. mutans, prevalent in dental plaque.
摘要翻译：本发明涉及新的5-烷基磺酰基水杨酰胺及其使用方法。更具体地说，本发明涉及下式的化合物：其中Z是取代或未取代的6至30个碳原子的苯环，包括取代基，R是1至20个碳原子的取代或未取代的烷基磺酰基，包括替代品 X为选自-CN，-NO 2，-H，卤素，低级烷基或低级卤代烷基的基团。上述含有它们的化合物和组合物是广泛的微生物，特别是细菌的有效的防腐剂，并且对于在牙菌斑中普遍存在的微生物，特别是变形链球菌，令人惊奇地高度有效。

27. 发明申请

US20090300332A1 NON-DESTRUCTIVE SIDEBAND READING OF PROCESSOR STATE INFORMATION 有权
标题翻译：处理器状态信息的非破坏性边栏读取
公开(公告)号：US20090300332A1
公开(公告)日：2009-12-03
申请号：US12130990
申请日：2008-05-30
申请人： Wallace P. Montgomery , David F. Tobias , Michael T. Clark
发明人： Wallace P. Montgomery , David F. Tobias , Michael T. Clark
IPC分类号： G06F9/30
CPC分类号： G06F11/3656 , G06F9/30003
摘要： A processor receives a command via a sideband interface on the processor to read processor state information, e.g., CPUID information. The sideband interface provides the command information to a microcode engine in the processor that executes the command to retrieve the designated processor state information at an appropriate instruction boundary and retrieves the processor state information. That processor information is stored in local buffers in the sideband interface to avoid modifying processor state. After the microcode engine completes retrieval of the information and the sideband interface command is complete, execution returns to the normal flow in the processor. Thus, the processor state information may be obtained non-destructively during processor runtime.
摘要翻译：处理器经由处理器上的边带接口接收命令以读取处理器状态信息，例如CPUID信息。边带接口向处理器中的微代码引擎提供命令信息，执行命令以在适当的指令边界检索指定的处理器状态信息并检索处理器状态信息。该处理器信息存储在边带接口中的本地缓冲区中，以避免修改处理器状态。在微代码引擎完成信息的检索并且边带接口命令完成之后，执行返回处理器中的正常流程。因此，可以在处理器运行时期间非破坏性地获得处理器状态信息。

28. 发明申请

US20090037932A1 MECHANISM FOR BROADCASTING SYSTEM MANAGEMENT INTERRUPTS TO OTHER PROCESSORS IN A COMPUTER SYSTEM 审中-公开
标题翻译：用于广播系统管理的机制与计算机系统中的其他处理器的中断
公开(公告)号：US20090037932A1
公开(公告)日：2009-02-05
申请号：US11831985
申请日：2007-08-01
申请人： Michael T. Clark , Jelena Ilic
发明人： Michael T. Clark , Jelena Ilic
IPC分类号： G06F9/44 , G06F13/24 , G06F15/177 , G06F15/76
CPC分类号： G06F13/24
摘要： A computer system includes a system memory, a plurality of processor cores, and an input/output (I/O) hub that may communicate with each of the processor cores. In response to detecting an occurrence of an internal system management interrupt (SMI), each of the processor cores may save to a system management mode (SMM) save state in the system memory, information corresponding to a source of the internal SMI. In response to detecting the internal SMI, each processor core may further initiate an I/O cycle to a predetermined port address within the I/O hub. The I/O hub may broadcast an SMI message to each of the processor cores in response to receiving the I/O cycle. Each of the processor cores may further save to the SMM save state in the system memory, respective internal SMI source information in response to receiving the broadcast SMI message.
摘要翻译：计算机系统包括系统存储器，多个处理器核心以及可与每个处理器核心通信的输入/输出（I / O）集线器。响应于检测到内部系统管理中断（SMI）的发生，每个处理器核心可以保存到系统存储器中的系统管理模式（SMM）保存状态，对应于内部SMI的源的信息。响应于检测到内部SMI，每个处理器核心可以进一步向I / O集线器内的预定端口地址发起I / O周期。响应于接收到I / O周期，I / O集线器可以向每个处理器核心广播SMI消息。响应于接收广播SMI消息，每个处理器核心可以进一步保存到系统存储器中的SMM保存状态，相应的内部SMI源信息。

29. 发明授权

US06968444B1 Microprocessor employing a fixed position dispatch unit 有权
标题翻译：微处理器采用固定位置调度单元
公开(公告)号：US06968444B1
公开(公告)日：2005-11-22
申请号：US10287301
申请日：2002-11-04
申请人： David E. Kroesche , Michael T. Clark
发明人： David E. Kroesche , Michael T. Clark
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/3822 , G06F9/3855
摘要： A microprocessor employing a fixed position dispatch unit. The microprocessor includes a plurality of execution units each corresponding to an issue position and configured to execute a common subset of instructions. At least a first one of the execution units includes extended logic for executing a designated instruction that others of the execution units may be incapable of executing. The microprocessor also includes a plurality of decoders coupled to the plurality of execution units. The plurality of decoders may provide positional information to cause the designated instruction to be routed to the first execution unit. Further, the microprocessor includes a dispatch control unit configured to dispatch during a dispatch cycle, the designated instruction for execution by the first execution unit based upon the positional information. The dispatch control unit may further dispatch one or more instructions within the common subset of instructions during the same dispatch cycle.
摘要翻译：采用固定位置调度单元的微处理器。微处理器包括多个执行单元，每个执行单元对应于发布位置并被配置为执行公共的指令子集。执行单元中的至少第一个包括用于执行指定指令的扩展逻辑，其他执行单元可能不能执行。微处理器还包括耦合到多个执行单元的多个解码器。多个解码器可以提供位置信息以使指定的指令被路由到第一执行单元。此外，微处理器包括调度控制单元，其被配置为在调度周期期间发送指定的指令，以由第一执行单元基于位置信息执行。调度控制单元还可以在相同调度周期内在指令的公共子集内调度一个或多个指令。

30. 发明授权

US06571330B1 Address size and operand size prefix overrides for default sizes defined by an operating mode of a processor 有权
标题翻译：由处理器的操作模式定义的默认大小的地址大小和操作数大小前缀替换
公开(公告)号：US06571330B1
公开(公告)日：2003-05-27
申请号：US09483560
申请日：2000-01-14
申请人： Kevin J. McGrath , Michael T. Clark
发明人： Kevin J. McGrath , Michael T. Clark
IPC分类号： G06F934
CPC分类号： G06F9/30192 , G06F9/30185 , G06F9/30189 , G06F9/342
摘要： A processor supports a processing mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, an instruction prefix may be coded into an instruction to override the default address and/or operand size. Thus, an address size of 32 bits may be used when desired, and an operand size of 64 bits may be used when desired.
摘要翻译：处理器支持默认地址大小大于32位，默认操作数大小为32位的处理模式。默认地址大小可以标称地指示为64位，尽管处理器的各种实施例可以在处理模式中实现超过32位，高达并包括64位的任何地址大小。可以通过将控制寄存器中的使能指示置于使能状态并且通过将段描述符中的第一操作模式指示和第二操作模式指示设置为预定状态来建立处理模式。另外，指令前缀可以被编码到用于覆盖默认地址和/或操作数大小的指令中。因此，如果需要，可以使用32位的地址大小，并且当需要时可以使用64位的操作数大小。

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