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1. 发明授权

US06510508B1 Translation lookaside buffer flush filter 有权
标题翻译：翻译后备缓冲器冲洗过滤器
公开(公告)号：US06510508B1
公开(公告)日：2003-01-21
申请号：US09595597
申请日：2000-06-15
申请人： Gerald D. Zuraski, Jr. , Michael T. Clark
发明人： Gerald D. Zuraski, Jr. , Michael T. Clark
IPC分类号： G06F1212
CPC分类号： G06F12/1027 , G06F2212/682 , G06F2212/683
摘要： A translation lookaside buffer (TLB) flush filter. In one embodiment, a central processing unit includes a TLB for storing recent address translations. A TLB flush filter monitors blocks of memory from which address translations have been loaded and cached in the TLB. The TLB flush filter is configured to detect if any of the underlying address translations in memory have changed. If no changes have occurred, the TLB flush filter may then prevent a flush of the TLB following the next context switch. If changes have occurred to the underlying address translations, the TLB flush filter may then allow a flush of the TLB following a context switch.
摘要翻译：翻译后备缓冲器（TLB）冲洗过滤器。在一个实施例中，中央处理单元包括用于存储最近地址转换的TLB。 TLB刷新过滤器监视在TLB中加载并缓存地址转换的内存块。 TLB刷新过滤器被配置为检测内存中的任何底层地址转换是否已更改。如果没有发生更改，则TLB刷新过滤器可能阻止在下一个上下文切换之后刷新TLB。如果底层地址转换发生更改，则TLB刷新过滤器可以允许在上下文切换之后刷新TLB。

2. 发明授权

US06446189B1 Computer system including a novel address translation mechanism 有权
标题翻译：计算机系统包括一种新颖的地址转换机制
公开(公告)号：US06446189B1
公开(公告)日：2002-09-03
申请号：US09323321
申请日：1999-06-01
申请人： Gerald D. Zuraski, Jr. , Frederick D. Weber , William A. Hughes , William K. Lewchuk , Scott A. White , Michael T. Clark
发明人： Gerald D. Zuraski, Jr. , Frederick D. Weber , William A. Hughes , William K. Lewchuk , Scott A. White , Michael T. Clark
IPC分类号： G06F1200
CPC分类号： G06F12/1054
摘要： A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e.g., a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU. The BIU includes address translation circuitry, a multiplexer, and gating logic, and returns the physical address corresponding to the linear address to the cache unit. The cache unit stores the physical address and the linear address within the TLB. The processor may also include a programmable control register and a microexecution unit. Upon detecting a change in state of an external masking signal, the microexecution unit may flush the contents of the TLB and modify a masking bit within the control register to reflect a new state of the masking signal.
摘要翻译：呈现包括耦合到总线接口单元（BIU）的高速缓存单元的处理器。地址信号选择和屏蔽功能由BIU内的电路而不是在高速缓存单元内执行，而由BIU生成的物理地址存储在TLB内。结果，从高速缓存单元内的临界速度路径消除了地址信号选择和屏蔽电路（例如，多路复用器和门控逻辑），从而允许高速缓存单元的操作速度增加。高速缓存单元存储数据项，并产生与所接收的线性地址对应的数据项。缓存单元内的翻译后备缓冲器（TLB）存储多个线性地址和对应的物理地址。当在TLB内没有找到与接收到的线性地址对应的物理地址时，高速缓存单元将线性地址传递给BIU。 BIU包括地址转换电路，多路复用器和门控逻辑，并将对应于线性地址的物理地址返回到高速缓存单元。高速缓存单元存储TLB内的物理地址和线性地址。处理器还可以包括可编程控制寄存器和微执行单元。在检测到外部屏蔽信号的状态变化时，微执行单元可以刷新TLB的内容并修改控制寄存器内的屏蔽位以反映掩蔽信号的新状态。

3. 发明申请

US20090177866A1 SYSTEM AND METHOD FOR FUNCTIONALLY REDUNDANT COMPUTING SYSTEM HAVING A CONFIGURABLE DELAY BETWEEN LOGICALLY SYNCHRONIZED PROCESSORS 审中-公开
标题翻译：功能冗余计算系统的系统和方法，具有逻辑同步处理器之间的可配置延迟
公开(公告)号：US20090177866A1
公开(公告)日：2009-07-09
申请号：US11970793
申请日：2008-01-08
申请人： Michael L. Choate , Mark D. Nicol , Michael T. Clark , Scott A. White , Gregory A. Lewis , Todd Foster , Gerald D. Zuraski, JR.
发明人： Michael L. Choate , Mark D. Nicol , Michael T. Clark , Scott A. White , Gregory A. Lewis , Todd Foster , Gerald D. Zuraski, JR.
IPC分类号： G06F9/30
CPC分类号： G06F11/1687 , G06F11/1641 , G06F11/1695
摘要： A method of operating a computer system. A first processor sends a first unit of binary information to an input/output (I/O) unit. The I/O unit then conveys the first unit of binary information to a functional unit in the computer system. A system response from the functional unit is then received by the I/O unit, which forwards the system response to the first processor. The system response is also stored in a first buffer. After a predetermined delay time has elapsed, the system response is then forwarded to the second processor.
摘要翻译：一种操作计算机系统的方法。第一处理器将二进制信息的第一单元发送到输入/输出（I / O）单元。然后，I / O单元将第二单元的二进制信息传送到计算机系统中的功能单元。然后由I / O单元接收来自功能单元的系统响应，该单元将系统响应转发给第一处理器。系统响应也存储在第一缓冲器中。在经过预定的延迟时间之后，系统响应被转发到第二处理器。

4. 发明授权

US07373484B1 Controlling writes to non-renamed register space in an out-of-order execution microprocessor 有权
标题翻译：控制对无序执行微处理器中的未重命名寄存器空间的写入
公开(公告)号：US07373484B1
公开(公告)日：2008-05-13
申请号：US10755692
申请日：2004-01-12
申请人： Arun Radhakrishnan , Benjamin T. Sander , Michael A. Filippo , Michael T. Clark , David E. Kroesche
发明人： Arun Radhakrishnan , Benjamin T. Sander , Michael A. Filippo , Michael T. Clark , David E. Kroesche
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3013 , G06F9/384
摘要： A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.
摘要翻译：控制对未重新命名的寄存器空间的写入操作的方法包括：接收对非重命名寄存器空间内的给定寄存器的写操作。该方法还包括确定是否存在对给定寄存器的挂起写入操作。响应于确定对给定寄存器的挂起写入操作存在，该方法包括阻止对给定寄存器的写入操作被调度。然而，响应于确定对给定寄存器的挂起写操作不存在，该方法包括允许对给定寄存器的写操作进行调度。此外，如果对给定寄存器的挂起写入操作不存在，则该方法包括允许对未重新命名的寄存器空间内的不同寄存器的后续写入操作进行调度。

5. 发明授权

US06973562B1 Establishing an operating mode in a processor 有权
标题翻译：在处理器中建立操作模式
公开(公告)号：US06973562B1
公开(公告)日：2005-12-06
申请号：US09483101
申请日：2000-01-14
申请人： Kevin J. McGrath , Michael T. Clark
发明人： Kevin J. McGrath , Michael T. Clark
IPC分类号： G06F9/34 , G06F9/318 , G06F9/30
CPC分类号： G06F9/30189 , G06F9/30185 , G06F9/342
摘要： A processor supports a processing mode in which the address size is greater than 32 bits and the operand size may be 32 or 64 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state).
摘要翻译：处理器支持地址大小大于32位的处理模式，操作数大小可以是32位或64位。地址大小可以名义上表示为64位，尽管在处理模式下，处理器的各种实施例可以实现超过32位，高达并包括64位的任何地址大小。可以通过将控制寄存器中的使能指示置于使能状态并且通过将段描述符中的第一操作模式指示和第二操作模式指示设置为预定状态来建立处理模式。可以使用第一操作模式指示和第二操作模式指示的其他组合来提供与x86处理器架构兼容的32位和16位处理的兼容性模式（使能指示保持在使能状态）。

6. 发明授权

US06898697B1 Efficient method for mode change detection and synchronization 有权
标题翻译：用于模式变化检测和同步的高效方法
公开(公告)号：US06898697B1
公开(公告)日：2005-05-24
申请号：US10113387
申请日：2002-03-29
申请人： Hongwen Gao , Chetana N. Keltcher , Michael T. Clark
发明人： Hongwen Gao , Chetana N. Keltcher , Michael T. Clark
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/52 , G06F12/02 , G06F13/00
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/30101 , G06F9/342 , G06F9/3861
摘要： A processor is configured to operate in a modes which utilize segmentation and which do not utilize segmentation. The processor includes circuitry which is configured to detect and respond to mode and state changes. The circuitry is configured to determine whether a segmentation state of the processor changes in response to execution of a control transfer operation. If the segmentation state does not change as a result of the transfer instruction, execution of instructions may continue sequentially and a corresponding first check performed. However, if the segmentation state does change as a result of the transfer instruction, a flush of the pipeline is initiated prior to performing a corresponding second check. When a first mode of operation is detected a limit check may be performed, while a canonical check may performed when a second mode of operation is detected. A special register is defined which is configured to indicate changes in segmentation state subsequent to a control transfer operations. A read of the special register may then be performed in order to determine whether a state change is indicated.
摘要翻译：处理器被配置为以利用分段并且不利用分段的模式操作。处理器包括被配置为检测并响应模式和状态改变的电路。电路被配置为确定处理器的分段状态是否响应于控制传送操作的执行而改变。如果作为传送指令的结果，分段状态不改变，则指令的执行可以顺序地继续进行并进行相应的第一检查。然而，如果作为转移指令的结果，分段状态确实改变，则在执行相应的第二次检查之前启动流水线的刷新。当检测到第一操作模式时，可以执行极限检查，而当检测到第二操作模式时可以执行规范检查。定义特殊寄存器，其被配置为指示在控制传送操作之后的分段状态的改变。然后可以执行特殊寄存器的读取，以便确定是否指示状态改变。

7. 发明授权

US06178956B2 Automotive fluid control system with pressure balanced solenoid valve 有权
标题翻译：具有压力平衡电磁阀的汽车流体控制系统
公开(公告)号：US06178956B2
公开(公告)日：2001-01-30
申请号：US09194346
申请日：1998-11-19
申请人： Christian Steinmann , Michael J. Covey , Thomas D. Herrington , Michael T. Clark , John W. Dillon , Steven J. Roskowski , Keith D. Marsh
发明人： Christian Steinmann , Michael J. Covey , Thomas D. Herrington , Michael T. Clark , John W. Dillon , Steven J. Roskowski , Keith D. Marsh
IPC分类号： F02M2507
CPC分类号： F02M35/10222 , F02M26/21 , F02M26/48 , F02M26/53 , F02M26/67 , F02M26/72 , F02M26/74 , F02M35/10019 , F02M35/10321 , F02M35/10386 , F02M35/1045
摘要： An automotive fluid control system with pressure balanced solenoid valve [24] and fluid mixing housing [22] is disclosed. The solenoid valve [24] is preferably used in an EGR (exhaust gas circulation) fluid control system, although the valve may be used in other vehicle fluid control systems, such as an engine block cooling liquid control system. A poppet member [84] of an EGR valve is pressured balanced such that only a light spring [170] and armature [88] are needed to control the positioning of the poppet member [84]. Magnetic and inductance sensors [184, 282] are used to accurately determine the position of the poppet member. The fluid mixing housing [22] homogeneously mixes first and second fluids. A portion of a main first fluid flow is funneled off and mixed in the housing [22] with a second fluid prior to being returned to the main fluid flow. Ideally, the housing [22] has a circumferentially extending channel [95] for intercepting, funnelling and mixing the captured portion of the main first fluid flow with the second fluid flow. Also, a solenoid subassembly [82] is disclosed which can mate with a variety of different valve housings [22] and which is adapted to mount on various engine configurations.
摘要翻译：公开了一种具有压力平衡电磁阀[24]和流体混合壳体[22]的汽车流体控制系统。电磁阀[24]优选用于EGR（排气循环）流体控制系统，尽管该阀可用于其他车辆流体控制系统，例如发动机缸体冷却液控制系统。 EGR阀的提升阀构件[84]被加压平衡，使得只需要一个弹簧[170]和电枢[88]来控制提升阀构件[84]的定位。磁性和电感传感器[184,282]用于准确地确定提升阀构件的位置。流体混合壳体[22]均匀混合第一和第二流体。主要第一流体流的一部分在被返回到主流体流之前用第二流体漏出并在壳体[22]中混合。理想地，壳体22具有周向延伸的通道，用于拦截，漏斗和混合主要第一流体流的捕获部分与第二流体流。此外，公开了一种螺线管子组件[82]，其可以与各种不同的阀壳体[22]配合，并且其适于安装在各种发动机构造上。

8. 发明授权

US5015627A Stabilized somatotropin for parenteral administration 失效
标题翻译：稳定的生长激素用于肠胃外给药
公开(公告)号：US5015627A
公开(公告)日：1991-05-14
申请号：US555970
申请日：1990-07-20
申请人： Thomas O. Lindsey , Michael T. Clark
发明人： Thomas O. Lindsey , Michael T. Clark
IPC分类号： A61K9/00 , A61K38/27 , A61K47/48
CPC分类号： A61K9/0024 , A61K38/27 , A61K47/48238
摘要： A stabilized somatotropin peptide aldehyde complex which provides prolonged release of the somatotropin and enhanced feed efficiency. The complex is prepared by dissolving the somatotropin and peptide aldehyde in water, isolating the complex from the aqueous solution, and crystalizing the product from alcohol. Specifically, the complex comprises porcine somatotropin and leupeptin and is particularly useful for enhancing feed efficiency in swine.
摘要翻译：稳定的生长激素肽醛复合物，其提供生长激素的延长释放和提高的饲料效率。通过将生长激素和肽醛溶解在水中，从水溶液中分离复合物，并从醇中使产物结晶来制备复合物。具体来说，复合物包括猪生长激素和亮抑酶肽，并且特别可用于提高猪的饲料效率。

9. 发明授权

US4440564A Heterocyclic pentalenes as herbicides 失效
标题翻译：杂环萜烯作为除草剂
公开(公告)号：US4440564A
公开(公告)日：1984-04-03
申请号：US418369
申请日：1982-09-15
申请人： Michael T. Clark , Ian J. Gilmore
发明人： Michael T. Clark , Ian J. Gilmore
IPC分类号： A01N43/90 , C07D515/04 , C07D515/06 , C07D515/12 , C07D515/16 , C07D517/04 , C07D517/06 , C07D517/12 , C07D517/16 , A01N43/02
CPC分类号： C07D515/04 , A01N43/90 , C07D515/06 , C07D517/04 , C07D517/06 , C07D517/08
摘要： Use as herbicides of, and herbicidal compositions containing as active ingredients, compounds of the formula: ##STR1## wherein the symbols have assigned meanings.
摘要翻译：作为含有作为活性成分的除草剂的除草剂可用作下式化合物：其中符号具有分配的含义。

10. 发明授权

US4163793A Use of certain thiophenecarbaldehyde phenylhydrazones as fungicides 失效
标题翻译：使用某些噻吩甲醛苯腙作为杀菌剂
公开(公告)号：US4163793A
公开(公告)日：1979-08-07
申请号：US921651
申请日：1978-07-03
申请人： Michael T. Clark , Pieter Ten Haken
发明人： Michael T. Clark , Pieter Ten Haken
IPC分类号： A01N35/10 , A01N37/28 , A01N43/06 , A01N43/30 , A01N43/36 , A01N43/40 , C07D207/32 , C07D207/335 , C07D213/53 , C07D307/52 , C07D317/66 , C07D333/22 , C07D333/62 , A01N9/12
CPC分类号： C07D207/335 , A01N35/10 , A01N37/28 , A01N43/06 , A01N43/30 , A01N43/36 , A01N43/40 , C07C251/72 , C07D213/53 , C07D307/52 , C07D317/66 , C07D333/22 , C07D333/62
摘要： Certain thiophenecarbaldehyde phenylhydrazones are used to control unwanted fungi.
摘要翻译：某些噻吩甲醛苯腙用于控制不需要的真菌。

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