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21. 发明申请

US20050110085A1 Dual gate finfet 有权
标题翻译：双门finfet
公开(公告)号：US20050110085A1
公开(公告)日：2005-05-26
申请号：US10717737
申请日：2003-11-20
申请人： Huilong Zhu , Jochen Beintner , Bruce Doris , Ying Zhang
发明人： Huilong Zhu , Jochen Beintner , Bruce Doris , Ying Zhang
IPC分类号： H01L21/336 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7856
摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.
摘要翻译：包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。每个FET包括沿半导体（例如，硅）翅片的一侧的器件栅极和沿鳍片相对的背偏置栅极。背偏置栅极电介质的不同之处在于器件栅极电介质的材料和/或厚度。可以通过调整背偏置栅极电压来调整器件阈值。

22. 发明授权

US06853025B2 Trench capacitor with buried strap 失效
标题翻译：带埋地带的沟槽电容器
公开(公告)号：US06853025B2
公开(公告)日：2005-02-08
申请号：US10248801
申请日：2003-02-20
申请人： Helmut Tews , Jochen Beintner , Stephan Kudelka
发明人： Helmut Tews , Jochen Beintner , Stephan Kudelka
IPC分类号： H01L21/20 , H01L21/8242 , H01L27/108 , H01L33/00
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.
摘要翻译：公开了一种具有改进带的沟槽电容器。带子位于电容器顶表面之上。由套环和储存板的顶表面形成的沟槽电容器的顶表面是平面的。通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。这样可以提高表带的可靠性和设备性能。

23. 发明授权

US06297530B1 Self aligned channel implantation 失效
标题翻译：自对准通道植入
公开(公告)号：US06297530B1
公开(公告)日：2001-10-02
申请号：US09418181
申请日：1998-12-28
申请人： Hiroyuki Akatsu , Yujun Li , Jochen Beintner
发明人： Hiroyuki Akatsu , Yujun Li , Jochen Beintner
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/823412 , H01L29/105
摘要： A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.
摘要翻译：短沟道绝缘栅场效应晶体管在半导体本体内部具有与晶体管相同的导电类型的掩埋层，但具有较高的杂质浓度。掩埋层在沟道区下方，并且基本上只延伸晶体管的漏极和源极区之间的距离。形成器件的过程在栅极下方的区域提供高浓度，以抑制横向耗尽区域膨胀，同时保持垂直方向上的逐渐连接。

24. 发明授权

US06177698B1 Formation of controlled trench top isolation layers for vertical transistors 失效
标题翻译：形成用于垂直晶体管的受控沟槽顶部隔离层
公开(公告)号：US06177698B1
公开(公告)日：2001-01-23
申请号：US09461599
申请日：1999-12-15
申请人： Ulrike Gruening , Jochen Beintner , Dirk Tobben , Gill Lee , Oswald Spindler , Zvonimir Gabric
发明人： Ulrike Gruening , Jochen Beintner , Dirk Tobben , Gill Lee , Oswald Spindler , Zvonimir Gabric
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L21/02126 , H01L21/02271 , H01L21/02304 , H01L21/31612 , H01L27/10876
摘要： A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.
摘要翻译：用于控制用于半导体器件的沟槽中的隔离层厚度的方法包括以下步骤：提供在其中形成的导电材料的沟槽，在导电材料上方的沟槽的侧壁上形成衬垫，在掩埋带上沉积选择性氧化物沉积层，侧壁，选择性氧化物沉积层以比在侧壁和顶表面的衬垫上更高的速率选择性地在导电材料上生长，并且除去与导电体接触的部分之外的选择性氧化物沉积层以形成隔离层沟槽中的导电材料。还包括当晶体管形成时，通过使衬底凹陷来制造垂直晶体管以允许晶体管沟道和掩埋带外扩散之间的重叠增加的方法。还公开了一种半导体器件。

25. 发明授权

US6143599A Method for manufacturing memory cell with trench capacitor 有权
标题翻译：具有沟槽电容器的存储单元的制造方法
公开(公告)号：US6143599A
公开(公告)日：2000-11-07
申请号：US235621
申请日：1999-01-22
申请人： Byeong Y. Kim , Carl Radens , Jochen Beintner
发明人： Byeong Y. Kim , Carl Radens , Jochen Beintner
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A memory cell includes a transistor and a capacitor that is a doped polysilicon filled trench. A doped polycrystalline strap provides a low resistance connection between a source region of the transistor and the polysilicon fill and is shaped to overlie both a top surface and a side surface of the source region of the transistor.
摘要翻译：存储单元包括晶体管和作为掺杂多晶硅填充沟槽的电容器。掺杂的多晶带提供了晶体管的源极区域和多晶硅填充物之间的低电阻连接，并且被成形为覆盖晶体管的源极区域的顶表面和侧表面。

26. 发明授权

US07785944B2 Method of making double-gated self-aligned finFET having gates of different lengths 失效
标题翻译：制造具有不同长度的栅极的双门控自对准finFET的方法
公开(公告)号：US07785944B2
公开(公告)日：2010-08-31
申请号：US12077973
申请日：2008-03-24
申请人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
发明人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.
摘要翻译：提供了一种制造门控半导体器件的方法。这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体区域具有第一侧和第二侧，例如远离第一侧。第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。在一个实施例中，第二栅极长度可以比第一栅极长度短。在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

27. 发明授权

US07666741B2 Corner clipping for field effect devices 有权
标题翻译：场效应装置的角剪
公开(公告)号：US07666741B2
公开(公告)日：2010-02-23
申请号：US11333109
申请日：2006-01-17
申请人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
发明人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
IPC分类号： H01L21/336
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/66795 , H01L29/7853
摘要： A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NH4OH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.
摘要翻译：提出了一种用于制造非平面场效应器件的方法。该方法包括生产Si基材料Fin结构，其具有与Si Fin结构的{111}晶面基本上平行的顶表面，并且用含有氢氧化铵（NH 4 OH）的溶液蚀刻Si Fin结构）。以这种方式，由于各种Si基材料结晶面的氢氧化铵中的蚀刻速率不同，Fin结构上的拐角被限制，Fin结构的水平和垂直平面之间的角度增加。然后制造具有夹角或圆角的FinFET器件以完成。在典型的实施例中，FinFET器件被选择为绝缘体上硅（SOI）器件。

28. 发明申请

US20090101995A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20090101995A1
公开(公告)日：2009-04-23
申请号：US12342655
申请日：2008-12-23
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

29. 发明授权

US07348641B2 Structure and method of making double-gated self-aligned finFET having gates of different lengths 有权
标题翻译：制造具有不同长度的栅极的双门控自对准finFET的结构和方法
公开(公告)号：US07348641B2
公开(公告)日：2008-03-25
申请号：US10711182
申请日：2004-08-31
申请人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
发明人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.
摘要翻译：提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸，所述主体具有与所述第一侧相对的第一侧和第二侧。门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。在一个实施例中，第一栅极和第二栅极彼此电隔离。在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

30. 发明申请

US20070166900A1 Device fabrication by anisotropic wet etch 失效
标题翻译：通过各向异性湿法蚀刻的器件制造
公开(公告)号：US20070166900A1
公开(公告)日：2007-07-19
申请号：US11333108
申请日：2006-01-17
申请人： Yujun Li , Kenneth Settlemyer , Jochen Beintner
发明人： Yujun Li , Kenneth Settlemyer , Jochen Beintner
IPC分类号： H01L21/8232 , H01L21/335 , H01L21/84 , H01L21/00
CPC分类号： H01L21/84 , H01L21/30608 , H01L27/1203 , H01L29/045 , H01L29/66772 , H01L29/66818 , H01L29/785
摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
摘要翻译：提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。制造基于Si的材料基座，其顶表面和其侧壁的取向方向基本上平行于基座和支撑构件的选定结晶平面。用包含氢氧化铵的各向异性溶液湿式蚀刻基座。基座的侧壁变小，在基座上形成截面减小的部分。选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

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