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21. 发明授权

US5875152A Address transition detection circuit for a semiconductor memory capable of detecting narrowly spaced address changes 失效
标题翻译：用于能够检测窄间隔地址变化的半导体存储器的地址转换检测电路
公开(公告)号：US5875152A
公开(公告)日：1999-02-23
申请号：US751513
申请日：1996-11-15
申请人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
发明人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18 , H03K5/1534 , G11C8/00 , H03K5/22
CPC分类号： H03K5/1534 , G11C7/22 , G11C8/18
摘要： The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input. The second circuit responsive to the change signal at the input generates an initialize command at the output. The circuit provides a second state at the output of the first circuit, for all including the last received in a series of change signals. This assures that all address transitions have been detected before a memory access is allowed.
摘要翻译：本发明提供一种新的（ATD）地址转换检测电路，用于具有任意数量的地址线的地址总线。公开了一种包括第一和第二电路和间隔定时器的ATD电路。第一电路具有第一和第二输入和输出。第一电路在第一输入端接收对应于地址总线的一个或多个地址中的转变的改变信号。作为响应，第一电路的输出从初始第一状态转变到第二状态。第一电路还响应于第二输入端的复位命令将输出返回到第一状态。间隔定时器具有耦合到第一电路的第二输入和输入的输出。响应于输入的初始化命令的间隔定时器启动定时间隔，并且在定时间隔之后在输出端产生复位命令。第二电路具有耦合到间隔定时器和输入的输入的输出。响应于输入端的变化信号的第二电路在输出端产生初始化命令。该电路在第一电路的输出处提供第二状态，包括在一系列变化信号中最后接收的信号。这确保在允许存储器访问之前已经检测到所有地址转换。

22. 发明授权

US06493276B2 Word line boost circuit 有权
标题翻译：字线升压电路
公开(公告)号：US06493276B2
公开(公告)日：2002-12-10
申请号：US09355653
申请日：1999-08-02
申请人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145
摘要： An improved word line boost circuit suitable for use on integrated circuits such as flash memory devices includes a two step boosting circuit with a floating circuit node. A first circuit provides an initial boost of the output voltage from a precharged voltage. Part of the first circuit is floated, lessening a load on a second circuit. Then, the second circuit provides a second boost of the output voltage with increased power efficiency. A time delay separates the onset of the second boosting operation from the onset of the first boosting operation so as to define a two-step boost.
摘要翻译：适用于诸如闪存器件的集成电路的改进的字线升压电路包括具有浮动电路节点的两级升压电路。第一电路从预充电电压提供输出电压的初始升压。第一个电路的一部分浮起来，减轻了第二个电路的负载。然后，第二电路以提高的功率效率提供输出电压的第二升压。时间延迟将第二升压操作的开始与第一升压操作的开始分开，以便定义两步升压。

23. 发明授权

US6147910A Parallel read and verify for floating gate memory device 有权
标题翻译：并行读取和验证浮动栅极存储器件
公开(公告)号：US6147910A
公开(公告)日：2000-11-14
申请号：US386766
申请日：1999-08-31
申请人： Yu-Ming Hsu , Yin-Shang Liu , Chun-Hsiung Hung , Ray-Lin Wan , Y. T. Lin
发明人： Yu-Ming Hsu , Yin-Shang Liu , Chun-Hsiung Hung , Ray-Lin Wan , Y. T. Lin
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C2211/5621 , G11C2211/5624 , G11C2211/5642 , G11C7/1048
摘要： A page mode flash memory or floating gate memory device, including a page buffer based upon low current bit latches, and additional capabilities for parallel read and parallel program verify operations. The present device includes bit latch circuitry and/or method steps that facilitate such parallel operations and avoid data conflicts. Circuitry for separate read signals can serve to isolate the operations. Additionally, circuitry tied to the data verification signal can also be used. A diode type device can be used to isolate signal conditions that might indicate the cell does not need to be programmed. Bit-by-bit precharging of the bit lines can also be employed in order to save precharging power. Additionally, the large capacitance of the dataline might be used to delay discharging a particular dataline, and thereby allow a latch enabling signal to go high, thus eliminating the need for further isolation circuitry, or the like.
摘要翻译：页面模式闪速存储器或浮动栅极存储器件，包括基于低电流位锁存器的页面缓冲器，以及用于并行读取和并行程序验证操作的附加功能。本装置包括有利于这种并行操作并避免数据冲突的位锁存电路和/或方法步骤。用于单独读取信号的电路可用于隔离操作。此外，还可以使用与数据验证信号相关的电路。可以使用二极管类型的器件来隔离可能指示电池不需要编程的信号条件。为了节省预充电功率，也可以采用位线的逐位预充电。此外，数据线的大电容可能用于延迟放电特定数据线，从而允许锁存使能信号变高，从而不需要进一步的隔离电路等。

24. 发明授权

US5835414A Page mode program, program verify, read and erase verify for floating gate memory device with low current page buffer 失效
标题翻译：页面模式程序，使用低电流页面缓冲区的浮动存储器设备的程序验证，读取和擦除验证
公开(公告)号：US5835414A
公开(公告)日：1998-11-10
申请号：US718334
申请日：1996-10-01
申请人： Chun-Hsiung Hung , Ray-Lin Wan , Yu-Sui Lee
发明人： Chun-Hsiung Hung , Ray-Lin Wan , Yu-Sui Lee
IPC分类号： G11C7/10 , G11C11/56 , G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3445 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/34 , G11C16/3459 , G11C7/1078 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642 , G11C2216/14 , G11C7/1048
摘要： A page mode flash memory or floating gate memory device, includes a page buffer based on low current bit latches. The low current bit latches enable efficient program, program verify, read and erase verify processes during page mode operation. The array includes bit lines coupled with corresponding columns of cells in the array, and wordlines coupled with corresponding rows of cells in the array. Bit latches are coupled to respective bit lines to provide a page buffer. Control logic executes the steps of (1) setting a set of bit lines to a pre-charge voltage level (such as VDD or ground); (2) isolating the pre-charged bit line, applying a wordline voltage to the wordline of the page of cells to be sensed; and (3) responding to changes in the voltage levels of the bit lines (which are discharged if a memory cell is conductive) in response to the wordline voltage, to store a constant in the bit latches coupled to the bit lines on which the voltage levels of the bit lines passes a determinate threshold during the step of applying a wordline voltage. The bit lines are connected to the gate terminal of a pass transistor, so that when the turn on threshold of the pass transistor is passed on the bit line, the pass transistor if turned on, and the constant is loaded into the bit latch.
摘要翻译： PCT No.PCT / US96 / 10393 Sec。 371日期：1996年10月1日 102（e）1996年10月1日PCT PCT 1996年6月14日PCT公布。第WO97 / 48101号公报日期1997年12月18日页面模式闪存或浮动栅极存储器件，包括基于低电流位锁存器的页面缓冲器。低电流位锁存器可在页模式操作期间实现高效的程序，程序验证，读取和擦除验证过程。阵列包括与阵列中的单元格的相应列耦合的位线，以及与阵列中的相应单元格行耦合的字线。位锁存器耦合到相应的位线以提供页缓冲器。控制逻辑执行以下步骤：（1）将一组位线设置为预充电电压电平（例如VDD或地）; （2）隔离预充电位线，将字线电压施加到要感测的单元的页面的字线; 和（3）响应于字线电压响应于位线的电压电平的变化（如果存储器单元是导通的则它们被放电），以便在耦合到位线上的位锁存器中存储常数，在施加字线电压的步骤期间，位线的电平通过确定的阈值。位线连接到传输晶体管的栅极端子，使得当通过晶体管的导通阈值在位线上通过时，传输晶体管如果导通，并且常数被加载到位锁存器中。

25. 发明授权

US5748535A Advanced program verify for page mode flash memory 失效
标题翻译：高级程序验证页面模式闪存
公开(公告)号：US5748535A
公开(公告)日：1998-05-05
申请号：US612968
申请日：1996-03-04
申请人： Tien-Ler Lin , Kota Soejima , Jun Takahashi , Chun-Hsiung Hung , Kong-Mou Liou , Ray-Lin Wan
发明人： Tien-Ler Lin , Kota Soejima , Jun Takahashi , Chun-Hsiung Hung , Kong-Mou Liou , Ray-Lin Wan
IPC分类号： G11C16/04 , G11C16/32 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3436 , G11C16/0491 , G11C16/32 , G11C16/3445 , G11C16/3459
摘要： Flash EEPROM cell and array designs, and methods for programming the same result in efficient and accurate programming of a flash EEPROM chip. The flash EEPROM chip comprises a memory array including at least M rows and N columns of flash EEPROM cells. M word lines are each coupled to the flash EEPROM cells in one of the M rows of flash EEPROM cells. A plurality of bit lines are each coupled to the flash EEPROM cells in one of the N columns of flash EEPROM cells. A page buffer coupled to the plurality of bit lines supplies input data to N columns of flash EEPROM cells. Write control circuitry supplies programming voltages for programming input data to the flash EEPROM cells in response to the input data stored in the data input buffer. Verify circuitry automatically verifies programming of the page by resetting bits in the page buffer for each cell which passes.
摘要翻译： PCT No.PCT / US95 / 00077 Sec。 371日期：1996年3月4日 102（e）1996年3月4日PCT PCT 1995年1月5日PCT公布。公开号WO96 / 21227 日期1996年7月11日闪存EEPROM单元和阵列设计以及用于编程相同结果的快速EEPROM芯片的高效准确编程的方法。快闪EEPROM芯片包括至少包括M行和N列快闪EEPROM单元的存储器阵列。 M个字线各自耦合到M行的快闪EEPROM单元之一中的快闪EEPROM单元。多个位线各自耦合到快速EEPROM单元的N列之一中的快闪EEPROM单元。耦合到多个位线的页缓冲器将快速EEPROM单元的输入数据提供给N列。响应于存储在数据输入缓冲器中的输入数据，写控制电路提供用于将输入数据编程到闪存EEPROM单元的编程电压。验证电路通过复位通过的每个单元的页面缓冲区中的位来自动验证页面的编程。

26. 发明授权

US5691945A Technique for reconfiguring a high density memory 失效
标题翻译：重构高密度存储器的技术
公开(公告)号：US5691945A
公开(公告)日：1997-11-25
申请号：US605100
申请日：1996-03-01
申请人： Kong-Mou Liou , Tom Dang-Hsing Yiu , Ray-Lin Wan , Yao-Wu Cheng , Chun-Hsiung Hung , Ting-Chung Hu , Tien-Ler Lin
发明人： Kong-Mou Liou , Tom Dang-Hsing Yiu , Ray-Lin Wan , Yao-Wu Cheng , Chun-Hsiung Hung , Ting-Chung Hu , Tien-Ler Lin
IPC分类号： G11C8/08 , G11C8/10 , G11C8/12 , G11C29/00 , G11C7/00
CPC分类号： G11C29/76 , G11C8/08 , G11C8/10 , G11C8/12
摘要： A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.
摘要翻译： PCT No.PCT / US95 / 06990第 371日期1996年3月1日 102（e）1996年3月1日PCT 1995年5月31日PCT PCT。公开号WO96 / 38845 日期1996年12月5日用于提高高密度存储器件（例如闪存EEPROM）的制造成品率的灵活技术涉及重新配置具有由地址解码器选择的多个扇区的集成电路存储器阵列，以响应于N位字段一个地址如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器以防止对阵列中的剩余扇区的顺序寻址，同时对阵列解码器进行划分以禁用缺陷扇区。分割步骤包括配置扇区解码器以在阵列的另一半中的另外一个扇区替换阵列的一半中的缺陷扇区，其中，当m在1和N之间时，具有与缺陷扇区相同的N个地址位的Nm -1。

27. 发明授权

US06400634B1 Technique for increasing endurance of integrated circuit memory 有权
标题翻译：提高集成电路存储器耐久性的技术
公开(公告)号：US06400634B1
公开(公告)日：2002-06-04
申请号：US09029952
申请日：1999-06-18
申请人： Kong-Mou Liou , Ting-Chung Hu , Ray-Lin Wan , Fuchia Shone
发明人： Kong-Mou Liou , Ting-Chung Hu , Ray-Lin Wan , Fuchia Shone
IPC分类号： G11C800
CPC分类号： G11C16/3495 , G11C16/08
摘要： A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. A record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.
摘要翻译：一种方法提高了存储器单元阵列的耐久性，其具有根据存储器单元在性能容限内可以承受的变化周期的数量来指定的耐久性。该方法基于将阵列布置成多个扇区，并且分配用于存储数据结构的地址的子集，其预期将改变足以超过阵列中的存储器单元的指定耐久性的次数。保持指示多个扇区中的一个作为当前扇区的记录，将使用地址子集的访问定向到当前扇区，对对当前扇区的地址子集标识的存储器单元进行计数改变，以及改变当前扇区当变化的计数超过阈值时，到多个扇区中的另一个扇区。

28. 发明授权

US06285240B1 Low threshold MOS two phase negative charge pump 有权
标题翻译：低阈值MOS两相负电荷泵
公开(公告)号：US06285240B1
公开(公告)日：2001-09-04
申请号：US09381066
申请日：1999-09-10
申请人： Tzing-Huei Shiau , Yu-Shen Lin , Ray-Lin Wan
发明人： Tzing-Huei Shiau , Yu-Shen Lin , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/078
摘要： A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal, nominally the source, coupled to a first node, and the second channel terminal, nominally the drain, coupled to its gate and to a second node. A first capacitor has a first terminal coupled to the first node of the charge pump, and a second terminal adapted to receive a first clock signal. A second transistor has a first channel terminal coupled to the second node of the charge pump, and a second channel terminal coupled to its gate and to a third node. A second capacitor has a first terminal coupled to the second node, and a second terminal adapted to receive a second clock signal. The first and second transistors comprise a first region and a second region having a first conductivity type providing the first and second channel terminals respectively, a channel region in which the first and second regions are formed having a second conductivity type, and an isolation well having the first conductivity type in a semiconductor substrate. The first and second regions, the channel region and the isolation well form a parasitic bipolar junction transistor that has a threshold voltage. The channel region has a doping concentration establishing a threshold voltage for the MOS transistor which is less than the threshold voltage of the parasitic bipolar junction transistor. The clock signals have sloped rising and falling edges.
摘要翻译：三阱电荷泵包括以二极管配置连接的第一晶体管，其具有连接到第一节点的名义上为源极的第一通道端子，以及连接到其栅极和第二节点的标称地为漏极的第二通道端子。第一电容器具有耦合到电荷泵的第一节点的第一端子，以及适于接收第一时钟信号的第二端子。第二晶体管具有耦合到电荷泵的第二节点的第一通道端子和耦合到其栅极和第三节点的第二通道端子。第二电容器具有耦合到第二节点的第一端子和适于接收第二时钟信号的第二端子。第一和第二晶体管包括第一区域和第二区域，其具有分别提供第一和第二沟道端子的第一导电类型，其中形成有第二导电类型的第一和第二区域的沟道区域和具有第二导电类型的隔离阱，半导体衬底中的第一导电类型。第一和第二区域，沟道区域和隔离阱形成具有阈值电压的寄生双极结型晶体管。沟道区域具有建立MOS晶体管的阈值电压的掺杂浓度，其小于寄生双极结型晶体管的阈值电压。时钟信号具有倾斜的上升沿和下降沿。

29. 发明授权

US6104665A Enhanced word line driver to reduce gate capacitance for low voltage applications 有权
标题翻译：增强字线驱动器，以降低低电压应用的栅极电容
公开(公告)号：US6104665A
公开(公告)日：2000-08-15
申请号：US269983
申请日：1999-04-05
申请人： Chun Hsiung Hung , I-Long Lee , Tien-Shin Ho , Ray-Lin Wan
发明人： Chun Hsiung Hung , I-Long Lee , Tien-Shin Ho , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C8/00
CPC分类号： G11C16/08 , G11C8/08
摘要： An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance load of deselected enhanced word line drivers from the boost voltage generator. The reduction of capacitive loading decreases power consumption and shortens the voltage boost time of the memory device.
摘要翻译： PCT No.PCT / US98 / 25809 Sec。 371日期1999年4月5日 102（e）1999年4月5日PCT 1998年12月4日提交适用于集成电路的增强型字线驱动电路，例如具有升压的闪存器件，包括负载降低电路。响应于升高的电压，负载降低电路将取消选择的增强型字线驱动器的栅极电容负载与升压电压发生器去耦。电容负载的降低降低了功耗并缩短了存储器件的升压时间。

30. 发明授权

US5877616A Low voltage supply circuit for integrated circuit 失效
公开(公告)号：US5877616A
公开(公告)日：1999-03-02
申请号：US849676
申请日：1997-06-13
申请人： Ray-Lin Wan , Chun-Hsiung Hung
发明人： Ray-Lin Wan , Chun-Hsiung Hung
IPC分类号： G05F3/24 , G05F3/16
CPC分类号： G05F3/247
摘要： A low voltage supply circuit supplies an internal supply voltage in an integrated circuit, while consuming very little stand-by current, and providing substantial driving power to maintain the internal supply nodes at the desired voltage level. The low voltage supply circuit includes a first branch and a second branch. The first branch includes a pull-up circuit, a first transistor, a second transistor, and a reference circuit connected in series. The drain and the gate of the first transistor are connected to a first node. The pull-up circuit in the first branch is coupled between the first node and a power supply node. The drain and the gate of the second transistor are connected to a second node. The reference circuit is connected between the ground supply node of the integrated circuit and the second node, supplying a reference potential to the second node. The sources of the first and second transistors are coupled in common to a third node in the first branch. The second branch of the low voltage supply circuit includes a third transistor and a fourth transistor. The drain of the third transistor is coupled to a power supply node, the gate of the third transistor is connected to the first node in the first branch, and the source of the third transistor being connected to an output node for the low voltage supply circuit. The drain of the fourth transistor is coupled to the ground supply node, the gate of the fourth transistor is connected to the second node in the first branch, and the source of the fourth transistor is connected to the output node. Bias circuits induce a larger body effect in the fourth transistor than in the second transistor, so that the fourth transistor has a threshold voltage higher in absolute value than the second transistor. The bias circuits also induce a larger body effect in the third transistor than in the first transistor, so that the third transistor has a threshold voltage higher in absolute value than the first transistor.

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