专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明专利

JPH03131031A THIN-FILM WIRING, MANUFACTURE THEREOF AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03131031A
公开(公告)日：1991-06-04
申请号：JP26997289
申请日：1989-10-17
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , KAWABUCHI YASUSHI , ONUKI HITOSHI , SHIODA KATSUHIKO , FUKADA SHINICHI , NIHEI MASAYASU , MIYAZAKI KUNIO
IPC分类号： H01L21/3205 , H01L23/48 , H01L23/52
摘要： PURPOSE:To prevent the extension of a slit due to electro-migration by directly bringing a high melting-point substance layer having a specific melting point and a good conductive alloy layer into contact and unifying them. CONSTITUTION:A high melting-point substance layer 4 having the melting point of 1800K or higher and a good conductive alloy layer 5 are brought into contact directly and unified. That is, the high melting-point substance layer 4 and the good conductive alloy layer 5 are laminated directly without through an oxide film. These direct contact is formed by reducing a spontaneous oxide film shaped onto the high melting-point substance layer 4 by an additive added into the good conductive alloy layer 5 laminated onto the natural oxide film. When the alloy of an Al group is selected as the good conductive alloy 5, it is also effective that Cu, Pd, Hf, Ti, etc., are added into an Al wiring and a metallic element easy to be sufficiently bonded with oxygen such as Mg, Ca, Be, Na, and K is further added.

22. 发明专利

JPH02188922A ELECTRONIC DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02188922A
公开(公告)日：1990-07-25
申请号：JP602989
申请日：1989-01-17
申请人： HITACHI LTD
发明人： KAWABUCHI YASUSHI , ONUKI HITOSHI , MIYAZAKI KUNIO , SHIODA KATSUHIKO , SUWA MOTOHIRO , NIHEI MASAYASU , FUKADA SHINICHI , ITAGAKI TATSUO
IPC分类号： H01L23/52 , H01L21/3205
摘要： PURPOSE:To obtain a wiring material whose stress-migration-resistant property and electromigration-resistant property with reference to a wiring film are both excellent by a method wherein the wiring layer is constituted of a laminated film by an Al alloy and TiW or TiN and an Mg or Be film is formed at an interface between the Al alloy and the TiW or TiN. CONSTITUTION:In an electronics device having wiring films 4 to 6 on a semiconductor or insulator substrate 1, said wiring films 4 to 6 are constituted of a laminated film by an Al alloy 4 and TiW or Tin 5 and an Mg or Be film 6 is formed at an interface between the Al alloy 4 and the TiW or TiN 5. For example, an Al alloy 4 contains less than 5wt.% each of Pd, Pt, Si, Li, Be, Mg, Mn, Fe, Co, Ni, Cu, La and Ce and its remaining part is composed of Al, or TiW or TiN 5 contains less than 20wt.% of Mg or Be. when either Mg or Be or both are added in advance, the Al alloy 4 and the TiW or TiN 5 are laminated directly, and wiring films 4 to 6 are formed.

23. 发明专利

JPS62177985A THIN FILM THERMOELECTRIC CONVERSION ELEMENT 失效
公开(公告)号：JPS62177985A
公开(公告)日：1987-08-04
申请号：JP1795586
申请日：1986-01-31
申请人： HITACHI LTD
发明人： MIYAZAKI KUNIO , FUKADA SHINICHI , SUZUKI HITOSHI
IPC分类号： H01L35/08 , H01L35/32
摘要： PURPOSE:To enable a thin film thermoelectric conversion element to be available in a high temperature range by laminating a plurality of element substrates in which P-type and N-type thermoelectric substances are electrically connected at an end to become a high temperature side, and connecting in series the P-type and the N-type films of the respective substrates. CONSTITUTION:After an Ni 2 is metallized by a depositing method on the end face of a glass substrate 1 at a high temperature side, an Fe-Si-Mn film 3 of a P-type thermal substance is first formed on the side of the glass by a sputtering method. Further, an Fe-Si-Co film 4 of an N-type thermoelectric substance is sputtered to the other side face of the glass substrate 1 to form an element substrate 5. The substrates 5 are laminated through an inorganic adhesive 6. At this time, since P-type and N-type films between the adjacent substrates are electrically connected in series, conductive paste 7 is buried in the part of the layer 6 at the low temperature side. Further, a Cu plate 8 is bonded through an inorganic adhesive 9, and electrodes 10 are led from the ends of the P-type and N-type thermoelectric film.

24. 发明专利

JP2001044201A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001044201A
公开(公告)日：2001-02-16
申请号：JP21564699
申请日：1999-07-29
申请人： HITACHI LTD
发明人： KONISHI NOBUHIRO , OKUDAIRA SADAYUKI , FUKADA SHINICHI
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/304 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To improve the yield and reliability of a semiconductor integrated circuit device by improving the planarity of an insulating film on metal interconnections formed by a CMP(Chemical mechanical polishing) method, and suppressing short circuits of the metal interconnections formed by the CMP method. SOLUTION: In a process step where a sacrificial film 16 is formed on an insulating film 11b and interconnections buried in grooves 15 formed of the films 11b and 16 are formed by deposition of a titanium nitride film 14b (barrier film) and a conductive film 18, such as a copper film and polishing using a CMP method, the film 16 which is polished at a speed higher than for the film 18 is polished at the same time. The film 16 is formed by implanting boron ions into the surface of the film 11b.

25. 发明专利

JP2000323568A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000323568A
公开(公告)日：2000-11-24
申请号：JP13000299
申请日：1999-05-11
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SATO AKIRA , MIYAZAKI HIROSHI , FUKADA SHINICHI , AOKI HIDEO , OSHIMA TAKAFUMI
IPC分类号： H01L21/768 , H01L21/28
摘要： PROBLEM TO BE SOLVED: To reduce the dishing or erosion by removing a barrier metal film in wiring layer trenches formed into an insulation film and vias at lower parts thereof, etc., except their side walls, etc. SOLUTION: Wiring layer trenches 18 and vias 19 are formed into an insulation film on a semiconductor substrate 1 and a TiN barrier metal film 20 is deposited. Using the etch back method, this film 20 is etched back to remove the barrier metal film 20 on lower parts of the vias 19 and the surface, etc., of the insulation film, thereby forming a pattern of the barrier metal film 20 for side walls only in the trenches 18 and on the side walls of the vias 19 at the lower parts thereof. Wiring metal layers 21, 22 composed of Cu layers for seed layers are formed on a semiconductor substrate 1. This extremely reduces dishing and erosion and a high-performance and high-reliability semiconductor device can be manufactured.

26. 发明专利

JPH1041388A INTER-LAYER CONNECTION OF SEMICONDUCTOR INTEGRATED CIRCUIT WIRING 失效
公开(公告)号：JPH1041388A
公开(公告)日：1998-02-13
申请号：JP19729496
申请日：1996-07-26
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , KOBAYASHI NOBUYOSHI
IPC分类号： H01L21/28 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To lower the required film thickness of a wiring layer for filling up connection holes to lower required pressure for the fill up in a high pressure fill up technique, by forming this wiring layer in a three-layer structure composed of a lower wiring metal layer, high m.p. metal layer, and upper wiring metal layer thicker than the lower wiring layer in an order from a substrate. SOLUTION: A wiring layer for filling up connection holes 7 has a three layer structure composed of a lower wiring metal layer 8, high m.p. metal layer 9 formed by the directional sputtering, and upper wiring metal layer 10 thicker than the lower wiring layer in an order from a substrate. The holes 7 are covered with only the upper wiring layer 10 and filled up with the metal of this layer 10 with holding a high temp. and high pressure in this condition. After forming the holes 7 through a layer insulation film 6, e.g. an Al-Cu alloy- made lower wiring metal layer 8, TnN-made high m.p. metal liner layer 9 and AlCu alloy-made upper wiring metal layer 10 are formed and holes 7 are filled up with the Al alloy at 450 deg.C, 500atm.

27. 发明专利

JPH09129844A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH09129844A
公开(公告)日：1997-05-16
申请号：JP28095795
申请日：1995-10-27
申请人： HITACHI LTD
发明人： FUKUDA TAKUYA , KOBAYASHI NOBUYOSHI , NAKAMURA YOSHITAKA , SAITO MASAYOSHI , FUKADA SHINICHI , KAWAMOTO YOSHIFUMI
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To avoid imperfect exposure and electrical connection failure which are to be caused by a step-difference, without increasing the number of steps, by forming a capacitor on the uppermost layer of a plurality of metal wiring layers. SOLUTION: Wirings from specified external circuits to the respective memory cells (e.g. word lines, bit lines, plate electrode wirings), and inner wirings of the respective memory cells (e.g. wirings between transistors and capacitors) are separately arranged in a plurality of metal wiring layers. At this time, e.g. after wirings 21, 22 and 23 of a third metal wiring layer 24 are formed, a flattened insulating layer of the third layer is formed by using the same processes as a first layer 12 and a second layer 18. After that, a connection plug 27 to a storage node 27 is formed. A capacitor is formed and the uppermost layer 32 of a wiring layer is formed. Thereby, memory cells and the wiring layer of a peripheral circuit can be formed on the same plane. Hence, a step- difference damage is not generated at the time of lithography.

28. 发明专利

JPH08115965A METHOD AND APPARATUS FOR EVALUATING RELIABILITY OF THIN FILM WIRING 失效
公开(公告)号：JPH08115965A
公开(公告)日：1996-05-07
申请号：JP25319294
申请日：1994-10-19
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , KUDO KAZUE , MINEMURA TETSUO
IPC分类号： G01R31/26 , H01L21/66
摘要： PURPOSE: To provide a method and an apparatus for evaluating the conduction liftetime regardless of the length of thin film wiring. CONSTITUTION: In the reliability evaluation method, the conduction liftetime is determined by measuring the conduction time to be elapsed before the electric resistance of a thin film wiring sample of length L, having current application terminals at the opposite ends with resistance measuring terminals being arranged at an interval of (m) between the current application terminals, increases by a predetermined ratio or more from an initial value. When a relationship n(t0 , m1 )/L1 >=n(t0 , m2 )/L2 is satisfied for the sample conduction time t0 , the wiring length L1 , the number n(t0 , m1 ) of conduction liftetime samples within the interval m1 of the resistance measuring terminals, the wiring length L2 , and the number n(t0 , m2 ) of conduction liftetime samples within the interval m2 of the resistance measuring terminals, F(t0 , m1 , m2 )=n(t0 , m1 )/L1 is determined as an accumulated defect density F per unit length for the wiring length m(m1

29. 发明专利

JPH05144808A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH05144808A
公开(公告)日：1993-06-11
申请号：JP30762691
申请日：1991-11-22
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , FUKADA SHINICHI , KUDO KAZUE
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768
摘要： PURPOSE:To provide a semiconductor device employing a wiring of low wiring resistance by a method wherein the contamination of semiconductor by copper is prevented when a copper wiring is used for semiconductor thin film wiring. CONSTITUTION:A diffusion barrier layer 6, which is wider than a contact hole, is formed on the upper part of the conductor 5, which is buried in the contact hole 4, covering the end part of the buried conductor 5. An adhesion layer 7 and a copper wiring 8 are formed thereon. As a result, the quick diffusion of copper 8 on the interface between an insulating film 3 and the buried conductor 5 can be prevented, and the increase of wiring resistance can also prevented.

30. 发明专利

JPH0536692A LAMINATED WIRINGS FOR LSI AND FORMATION THEREOF 失效
公开(公告)号：JPH0536692A
公开(公告)日：1993-02-12
申请号：JP19149691
申请日：1991-07-31
申请人： HITACHI LTD
发明人： KUDO KAZUE , FUKADA SHINICHI , SUWA MOTOHIRO
IPC分类号： H01L21/3213 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To improve throwing power of an interlayer insulating film to wirings and to eliminate corrosion of a main wiring during processing by so forming a shape of a section perpendicular to a current direction of an uppermost layer of laminated wirings made of three or more layers in a curved shape that a protrusion side is disposed at an upper side. CONSTITUTION:A thermal oxide SiO2 film 5, a barrier layer 2, a main wiring 1 and an uppermost layer 3 are formed on an Si substrate 1. The wiring 1 is formed of Cu or a Cu alloy film, and the layers 2, 3 are formed of TiN films. The layer 3 is formed thicker than the layer 2. After the layer 3 is etched with resist as a mask, the resist is removed by a plasma asher. Further, with the layer 3 as a mask the wiring 1, the layer 2 are dry etched. In this case, the shape of the layer 3 is formed in a shape in which a protrusion is disposed at an upper side. Then, an interlayer insulating film 6 is formed several thousands Angstrom on the wiring by a plasma CVD method without removing the TiN of the layer 3. Thus, the shape of the main wiring is not altered, and throwing power of the insulating film is improved.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式