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21. 发明申请

US20080308936A1 METHOD AND STURCTURE FOR SELF-ALIGNED DEVICE CONTACTS 有权
标题翻译：自对准设备联系人的方法和工作
公开(公告)号：US20080308936A1
公开(公告)日：2008-12-18
申请号：US12194563
申请日：2008-08-20
申请人： Gregory Costrini , David M. Fried
发明人： Gregory Costrini , David M. Fried
IPC分类号： H01L23/532
CPC分类号： H01L29/458 , H01L21/76829 , H01L21/76897 , H01L21/84 , H01L27/12 , H01L29/41733 , H01L29/665 , H01L29/6656 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.
摘要翻译：公开了在触点下部具有部分自对准接触的半导体结构的实施例被扩大以降低电阻而不会影响器件的产量。另外，该结构可选地包含厚中间线（MOL）氮化物应力膜以增强载流子迁移率。形成结构的方法的实施例包括在接触的预期位置形成牺牲部分。该部分被图案化，使得其与栅电极自对准，并且仅占用用于将来接触的空间。一旦牺牲部分就位就可以沉积介质层（例如，可选的应力层，然后是层间电介质）。常规的接触光刻用于蚀刻通过介电层到牺牲部分的接触孔。然后选择性地去除牺牲部分以形成空腔，并且在空腔和接触孔中形成接触。

22. 发明申请

US20080026513A1 METHOD AND STRUCTURE FOR SELF-ALIGNED DEVICE CONTACTS 有权
标题翻译：自对准设备联系人的方法和结构
公开(公告)号：US20080026513A1
公开(公告)日：2008-01-31
申请号：US11460010
申请日：2006-07-26
申请人： Gregory Costrini , David M. Fried
发明人： Gregory Costrini , David M. Fried
IPC分类号： H01L21/84
CPC分类号： H01L29/458 , H01L21/76829 , H01L21/76897 , H01L21/84 , H01L27/12 , H01L29/41733 , H01L29/665 , H01L29/6656 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.
摘要翻译：公开了在触点下部具有部分自对准接触的半导体结构的实施例被扩大以降低电阻而不会影响器件的产量。另外，该结构可选地包含厚中间线（MOL）氮化物应力膜以增强载流子迁移率。形成结构的方法的实施例包括在接触的预期位置形成牺牲部分。该部分被图案化，使得其与栅电极自对准，并且仅占用用于将来接触的空间。一旦牺牲部分就位就可以沉积介电层（例如，任选的应力层，然后是层间电介质）。常规的接触光刻用于蚀刻通过介电层到牺牲部分的接触孔。然后选择性地去除牺牲部分以形成空腔，并且在空腔和接触孔中形成接触。

23. 发明授权

US06985384B2 Spacer integration scheme in MRAM technology 有权
标题翻译： MRAM技术中的间隔整合方案
公开(公告)号：US06985384B2
公开(公告)日：2006-01-10
申请号：US10261709
申请日：2002-10-01
申请人： Gregory Costrini , John Hummel , Kia-Seng Low , Igor Kasko , Frank Findeis , Wolfgang Raberg
发明人： Gregory Costrini , John Hummel , Kia-Seng Low , Igor Kasko , Frank Findeis , Wolfgang Raberg
IPC分类号： G11C11/18
CPC分类号： H01L43/12
摘要： A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.
摘要翻译：通过蚀刻由缓冲层，钉扎磁性层，隧道势垒层和自由磁性层组成的覆盖金属堆叠来制造磁阻存储器件。通过形成覆盖自由层和隧道屏障界面侧面的保护性间隔物，消除了在蚀刻过程期间与溅射金属接合短路的问题。在通过在阻挡层上停止的自由层的第一次蚀刻之后形成间隔物。在间隔物形成之后，进行第二次蚀刻以隔离该装置。器件隧道结的图案化使用一次性心轴方法制造，其能够在器件图案化工艺完成之后进行自对准接触。

24. 发明授权

US06974770B2 Self-aligned mask to reduce cell layout area 失效
标题翻译：自对准面罩减少细胞布局面积
公开(公告)号：US06974770B2
公开(公告)日：2005-12-13
申请号：US10600034
申请日：2003-06-20
申请人： Gregory Costrini , Kia-Seng Low , David L. Rath , Michael C. Gaidis , Walter Glashauser
发明人： Gregory Costrini , Kia-Seng Low , David L. Rath , Michael C. Gaidis , Walter Glashauser
IPC分类号： H01L21/60 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/76897 , H01L21/76834
摘要： Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.
摘要翻译：在相邻的金属化线之间蚀刻的自对准通孔和沟槽允许分配给通孔或沟槽的电介质衬底的面积显着减小，而不增加对相邻金属化线的电短路的可能性。

25. 发明授权

US06743642B2 Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology 失效
标题翻译：双层CMP工艺，提高MRAM技术中磁性堆叠的表面粗糙度
公开(公告)号：US06743642B2
公开(公告)日：2004-06-01
申请号：US10289488
申请日：2002-11-06
申请人： Gregory Costrini , John Hummel , Kia-Seng Low , Mahadevaiyer Krishnan
发明人： Gregory Costrini , John Hummel , Kia-Seng Low , Mahadevaiyer Krishnan
IPC分类号： H01L2100
CPC分类号： H01L43/12 , B82Y25/00 , B82Y40/00 , G11C11/16 , H01F10/26 , H01F10/3254 , H01F41/307 , H01L27/222
摘要： A method for manufacturing a magnetoresistive random access memory (MRAM) cell is disclosed, which alleviates the problem of Neel coupling caused by roughness in the interface between the tunnel junction layer and the magnetic layers. The method includes depositing first and second barrier layers on the conductor, wherein the first barrier layer has a polish rate different from that of the second barrier layer. The second barrier layer is then essentially removed by chemical mechanical polishing (CMP), leaving a very smooth and uniform first barrier layer. When the magnetic stack is then formed on the polished first barrier layer, interfacial roughness is not translated to the tunnel junction layer, and no corruption of magnetization is experienced.
摘要翻译：公开了一种用于制造磁阻随机存取存储器（MRAM）单元的方法，其减轻了由隧道结层和磁性层之间的界面中的粗糙度引起的Neel耦合的问题。该方法包括在导体上沉积第一和第二阻挡层，其中第一阻挡层具有与第二阻挡层不同的抛光速率。然后通过化学机械抛光（CMP）基本上除去第二阻挡层，留下非常平滑和均匀的第一阻挡层。当磁性堆叠形成在抛光的第一阻挡层上时，界面粗糙度不会转变为隧道结层，并且不会发生磁化腐蚀。

26. 发明授权

US06323127B1 Capacitor formed with Pt electrodes having a 3D cup-like shape with roughened inner and outer surfaces 失效
标题翻译：由具有3D杯状形状的Pt电极形成的电容器具有粗糙的内表面和外表面
公开(公告)号：US06323127B1
公开(公告)日：2001-11-27
申请号：US09599698
申请日：2000-06-22
申请人： Panayotis Andricacos , Gregory Costrini , David Edward Kotecki , Katherine Lynn Saenger
发明人： Panayotis Andricacos , Gregory Costrini , David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L214763
CPC分类号： H01L28/84 , H01L27/1085 , H01L28/65 , H01L28/91
摘要： A noble metal electrode structure having a cup-like, approximately cylindrical shape, roughened inner and outer surfaces, and a surface area of at least 1 sq. micron or greater is provided as well as a capacitor which includes the noble metal electrode as a bottom electrode. The high-surface area noble metal electrode is formed by electroplating into annular channels that have roughened sidewalls formed by the oxidation of vapor-deposited Si nuclei.
摘要翻译：提供具有杯状，大致圆筒形，粗糙内表面和至少1平方微米或更大的表面积的贵金属电极结构以及包括贵金属电极作为底部的电容器电极。高表面积贵金属电极通过电镀形成通过气相沉积的Si核的氧化形成的粗化侧壁的环形通道形成。

27. 发明授权

US5587045A Gettering of particles from an electro-negative plasma with insulating chuck 失效
标题翻译：用绝缘卡盘从电 - 负等离子体吸取颗粒
公开(公告)号：US5587045A
公开(公告)日：1996-12-24
申请号：US430040
申请日：1995-04-27
申请人： John H. Keller , Gregory Costrini
发明人： John H. Keller , Gregory Costrini
IPC分类号： H01J37/32 , H01L21/306
CPC分类号： H01J37/32174 , H01J37/32082 , H01J37/32623 , H01J37/32706 , H01J37/32963
摘要： Apparatus controls a wafer potential in a plasma system when the plasma is off to keep the wafer slightly negative at all times in order to reduce and eliminate the collection of charged particles on the wafer. The apparatus allows the wafer bias to be reduced to a small negative voltage and then holds that voltage. This greatly reduces the net positive flux to the wafer. A diode and a programmed power supply hold a minimum negative voltage on the back of the wafer electrode when the plasma density is decaying to zero.
摘要翻译：当等离子体关闭时，设备控制等离子体系统中的晶圆电位，以使晶片始终保持微小的负值，以便减少和消除晶片上带电粒子的收集。该装置允许将晶片偏压降低到小的负电压，然后保持该电压。这大大降低了晶片的净正通量。当等离子体密度衰减到零时，二极管和编程电源在晶片电极的背面保持最小的负电压。

28. 发明授权

US4933302A Formation of laser mirror facets and integration of optoelectronics 失效
标题翻译：形成激光镜面和光电集成
公开(公告)号：US4933302A
公开(公告)日：1990-06-12
申请号：US340195
申请日：1989-04-19
申请人： Gregory Costrini , Chakrapani G. Jambotkar
发明人： Gregory Costrini , Chakrapani G. Jambotkar
IPC分类号： H01L27/15 , G02B6/124 , H01S5/00 , H01S5/02 , H01S5/026 , H01S5/028 , H01S5/227
CPC分类号： H01S5/026 , G02B6/124 , H01S5/028 , H01S5/0205 , H01S5/0261 , H01S5/2272 , Y10S148/026 , Y10S148/095 , Y10S148/106
摘要： A planar process for fabricating an optoelectronic integrated circuit device is described. The process includes the in situ formation of laser diode mirror facets comprising the steps of providing a semi-insulating gallium arsenide substrate having thereon layers of n-doped gallium arsenide, n-doped aluminum gallium arsenide, and undoped gallium arsenide; patterning and etching the undoped gallium arsenide layer into a mandrel having substantially vertical walls; establishing insulator sidewalls on the vertical walls; removing the mandrel, thereby exposing the inner walls of the insulator sidewalls and leaving the insulator sidewalls self-standing; removing the aluminum gallium arsenide using the insulator sidewall as a mask; and forming a laser diode within the region between the insulator sidewalls and creating the mirror facets with the inner walls of the insulator sidewalls. Mirror facets formed in accordance with this process are substantially free of contaminants. The process is suitable for high level of monolithic integration, including the formation of other optical devices, such as waveguides, driver circuits, logic and other electronic circuits.

29. 发明授权

US07875550B2 Method and structure for self-aligned device contacts 有权
标题翻译：自对准设备触点的方法和结构
公开(公告)号：US07875550B2
公开(公告)日：2011-01-25
申请号：US12110465
申请日：2008-04-28
申请人： Gregory Costrini , David M. Fried
发明人： Gregory Costrini , David M. Fried
IPC分类号： H01L21/4763
CPC分类号： H01L29/458 , H01L21/76829 , H01L21/76897 , H01L21/84 , H01L27/12 , H01L29/41733 , H01L29/665 , H01L29/6656 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.
摘要翻译：公开了在接触件的下部具有部分自对准接触的半导体结构的实施例，以减小电阻而不会影响器件的产量。另外，该结构可选地包含厚中间线（MOL）氮化物应力膜以增强载流子迁移率。形成结构的方法的实施例包括在接触的预期位置形成牺牲部分。该部分被图案化，使得其与栅电极自对准，并且仅占用用于将来接触的空间。一旦牺牲部分就位就可以沉积介质层（例如，可选的应力层，然后是层间电介质）。常规的接触光刻用于蚀刻通过介电层到牺牲部分的接触孔。然后选择性地去除牺牲部分以形成空腔，并且在空腔和接触孔中形成接触。

30. 发明授权

US07605447B2 Highly manufacturable SRAM cells in substrates with hybrid crystal orientation 有权
标题翻译：具有混合晶体取向的基板中的高度可制造的SRAM单元
公开(公告)号：US07605447B2
公开(公告)日：2009-10-20
申请号：US11162780
申请日：2005-09-22
申请人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L29/06 , H01L29/04 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

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