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1. 发明授权

US06323127B1 Capacitor formed with Pt electrodes having a 3D cup-like shape with roughened inner and outer surfaces 失效
标题翻译：由具有3D杯状形状的Pt电极形成的电容器具有粗糙的内表面和外表面
公开(公告)号：US06323127B1
公开(公告)日：2001-11-27
申请号：US09599698
申请日：2000-06-22
申请人： Panayotis Andricacos , Gregory Costrini , David Edward Kotecki , Katherine Lynn Saenger
发明人： Panayotis Andricacos , Gregory Costrini , David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L214763
CPC分类号： H01L28/84 , H01L27/1085 , H01L28/65 , H01L28/91
摘要： A noble metal electrode structure having a cup-like, approximately cylindrical shape, roughened inner and outer surfaces, and a surface area of at least 1 sq. micron or greater is provided as well as a capacitor which includes the noble metal electrode as a bottom electrode. The high-surface area noble metal electrode is formed by electroplating into annular channels that have roughened sidewalls formed by the oxidation of vapor-deposited Si nuclei.
摘要翻译：提供具有杯状，大致圆筒形，粗糙内表面和至少1平方微米或更大的表面积的贵金属电极结构以及包括贵金属电极作为底部的电容器电极。高表面积贵金属电极通过电镀形成通过气相沉积的Si核的氧化形成的粗化侧壁的环形通道形成。

2. 发明授权

US5825609A Compound electrode stack capacitor 失效
标题翻译：复合电极堆叠电容器
公开(公告)号：US5825609A
公开(公告)日：1998-10-20
申请号：US636457
申请日：1996-04-23
申请人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
发明人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , H01G4/06
CPC分类号： H01L28/82 , H01L21/76849 , H01L21/7687 , H01L27/1085 , H01L28/91 , H01L28/55
摘要： This invention is directed to a semiconductor memory device including a storage element having a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.
摘要翻译：本发明涉及一种半导体存储器件，其包括在顶部（板）电极和底部（堆叠）电极之间具有铁电材料或电容器电介质材料的存储元件。特别地，本发明涉及堆叠电极的设计和制造，其被描述为化合物，因为它由两种或更多种材料组成，这两种或多种材料是单独图案化的（至少一种材料在沉积之前沉积和图案化其他），或者被布置成使得每个组分材料显着地有助于初始沉积铁电体或电容器电介质的区域。相对于相同尺寸的固体单材料电极，这些复合堆叠电极可以提供易于处理，更经济地使用贵金属材料以及潜在的增加的机械稳定性（例如抵抗小丘）。

3. 发明授权

US5712759A Sidewall capacitor with L-shaped dielectric 失效
公开(公告)号：US5712759A
公开(公告)日：1998-01-27
申请号：US577165
申请日：1995-12-22
申请人： Katherine Lynn Saenger , James H. Comfort , Alfred Grill , David Edward Kotecki
发明人： Katherine Lynn Saenger , James H. Comfort , Alfred Grill , David Edward Kotecki
IPC分类号： H01L21/02 , H01G4/002 , H01G4/008 , H01G4/06
CPC分类号： H01L28/82 , H01L28/40 , Y10T29/435
摘要： A capacitor structure with a generally L-shaped non-conductor having a horizontal portion and a vertical portion, the vertical portion defining a first opening formed therein; a generally U-shaped conductor formed within the first opening; and a generally L-shaped conductor formed exterior to the generally L-shaped non-conductor.

4. 发明授权

US06727174B1 Method for fabricating a dual-diameter electrical conductor 失效
标题翻译：制造双直径电导体的方法
公开(公告)号：US06727174B1
公开(公告)日：2004-04-27
申请号：US09643372
申请日：2000-08-22
申请人： David Edward Kotecki , Katherine Lynn Saenger
发明人： David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L214763
CPC分类号： H01L28/10 , H01L21/76877
摘要： The present invention discloses a multi-diameter electrical conductor for use as an embedded plug in a microelectronic device. The multi-diameter electrical conductor consists of a body portion which has a first diameter, and at least one neck portion in contact with the body portion that has at least a second diameter smaller than the first diameter. In a preferred embodiment, the multi-diameter conductor is a dual-diameter conductor providing electrical communication between an electrode and an active circuit element in a semiconductor structure and comprising a lower body portion and an upper neck portion. The conductive materials used in forming the body portion and the neck portion of the contact plug can be selected from doped polysilicon, refractory metals, metal silicides, low resistivity metals, noble metals and their alloys, adhesion layers, metallic diffusion barrier layers, and oxide and nitride diffusion barrier materials. In a preferred embodiment, the body portion is formed of a first conductive material while the neck portion is formed of a second conductive material. In an alternate embodiment, the body portion and the neck portion are formed of the same conductive material. In another alternate embodiment, the contact plug further includes an additional layer of a conductive material situated between the body portion and the neck portion formed of a material different than that used in forming the body portion and the neck portion. The additional layer of conductive material has a diameter not less than the diameter of the neck portion and not more than the diameter of the body portion.
摘要翻译：本发明公开了一种用于微电子器件中的嵌入式插头的多直径电导体。多直径电导体包括具有第一直径的主体部分和与主体部分接触的至少一个颈部部分，其至少具有小于第一直径的第二直径。在优选实施例中，多直径导体是提供电极和半导体结构中的有源电路元件之间的电连通并且包括下主体部分和上颈部部分的双直径导体。用于形成接触插塞的主体部分和颈部的导电材料可以选自掺杂多晶硅，难熔金属，金属硅化物，低电阻金属，贵金属及其合金，粘附层，金属扩散阻挡层和氧化物和氮化物扩散阻挡材料。在优选实施例中，主体部分由第一导电材料形成，而颈部由第二导电材料形成。在替代实施例中，主体部分和颈部由相同的导电材料形成。在另一替代实施例中，接触插塞还包括位于主体部分和颈部之间的导电材料的附加层，所述导电材料由与用于形成主体部分和颈部部分的材料不同的材料形成。附加的导电材料层的直径不小于颈部的直径，而不大于主体部分的直径。

5. 发明授权

US6131258A Sidewall capacitor with L-shaped dielectric 失效
标题翻译：具有L形电介质的侧壁电容器
公开(公告)号：US6131258A
公开(公告)日：2000-10-17
申请号：US908295
申请日：1997-08-07
申请人： Katherine Lynn Saenger , James H. Comfort , Alfred Grill , David Edward Kotecki
发明人： Katherine Lynn Saenger , James H. Comfort , Alfred Grill , David Edward Kotecki
IPC分类号： H01L21/02 , H01G7/00
CPC分类号： H01L28/82 , H01L28/40 , Y10T29/435
摘要： A capacitor structure with a generally L-shaped non-conductor having a horizontal portion and a vertical portion, the vertical portion defining a first opening formed therein; a generally U-shaped conductor formed within the first opening; and a generally L-shaped conductor formed exterior to the generally L-shaped non-conductor.
摘要翻译：一种具有大致L形非导体的电容器结构，具有水平部分和垂直部分，垂直部分限定形成在其中的第一开口; 形成在第一开口内的大致U形的导体; 以及在大致L形的非导体的外部形成的大致L形的导体。

6. 发明授权

US5998250A Compound electrode stack capacitor 失效
标题翻译：复合电极堆叠电容器
公开(公告)号：US5998250A
公开(公告)日：1999-12-07
申请号：US62031
申请日：1998-04-17
申请人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
发明人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： H01L28/82 , H01L21/76849 , H01L21/7687 , H01L27/1085 , H01L28/91 , H01L28/55
摘要： This invention is directed to a semiconductor memory device including a storage element comprising a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.
摘要翻译：本发明涉及一种半导体存储器件，其包括在顶部（板）电极和底部（堆叠）电极之间包括铁电材料或电容器电介质材料的存储元件。特别地，本发明涉及堆叠电极的设计和制造，其被描述为化合物，因为它由两种或更多种材料组成，这两种或多种材料是单独图案化的（至少一种材料在沉积之前沉积和图案化其他），或者被布置成使得每个组分材料显着地有助于初始沉积铁电体或电容器电介质的区域。相对于相同尺寸的固体单材料电极，这些复合堆叠电极可以提供易于处理，更经济地使用贵金属材料以及潜在的增加的机械稳定性（例如抵抗小丘）。

7. 发明授权

US06242321B1 Structure and fabrication method for non-planar memory elements 失效
标题翻译：非平面记忆元件的结构和制造方法
公开(公告)号：US06242321B1
公开(公告)日：2001-06-05
申请号：US09303595
申请日：1999-05-03
申请人： Raul Edmundo Acosta , James Hartfiel Comfort , Alfred Grill , David Edward Kotecki , Katherine Lynn Saenger
发明人： Raul Edmundo Acosta , James Hartfiel Comfort , Alfred Grill , David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L2176
CPC分类号： H01L27/10852 , H01L28/55
摘要： Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.
摘要翻译：用于存储器单元应用的结构，包括用于DRAM的电容器和来自FRAM的铁电存储器单元，其制造方法包括沉积铁电体或高ε电介质材料以完全填充空腔，其几何宽度是电学厚度的唯一决定因素最终装置中铁电或高ε电介质层的有效部分。在优选实施例中，沉积电介质的空腔由在电介质沉积之前的通过掩模镀层步骤中沉积和图案化的板和堆叠电极之间的间隙限定。

8. 发明授权

US6027966A Isolated sidewall capacitor 失效
标题翻译：隔离侧壁电容器
公开(公告)号：US6027966A
公开(公告)日：2000-02-22
申请号：US910179
申请日：1997-08-13
申请人： Katherine Lynn Saenger , James H. Comfort , Alfred Grill , David Edward Kotecki
发明人： Katherine Lynn Saenger , James H. Comfort , Alfred Grill , David Edward Kotecki
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L28/55 , H01L27/10852 , Y10T29/435
摘要： A capacitor structure is provided, with a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening.
摘要翻译：提供一种电容器结构，其中第一导体位于衬底的顶部，第一非导体位于第一导体之上，并且基本上与第一导体对准，第一导体和第一非导体具有形成在其中的第一开口，形成在第一开口中的导电侧壁间隔物，其中形成有第二开口的非导电侧壁隔离物和形成在第二开口中的第二导体。

9. 发明授权

US5932907A Method, materials, and structures for noble metal electrode contacts to silicon 失效
标题翻译：贵金属电极接触硅的方法，材料和结构
公开(公告)号：US5932907A
公开(公告)日：1999-08-03
申请号：US866459
申请日：1997-05-30
申请人： Alfred Grill , David Edward Kotecki , Katherine Lynn Saenger
发明人： Alfred Grill , David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L21/8242 , H01L27/112 , H01L27/04
CPC分类号： H01L27/10852
摘要： A layered structure is described incorporating a noble metal silicide, a noble metal and an oxygen-rich barrier layer between the noble metal silicide and noble metal. A silicon-contributing substrate may also be present in addition to or without the noble metal silicide. The invention overcomes a problem in fabricating capacitors containing high-epsilon dielectric materials or ferroelectric memory elements containing ferroelectric material, namely that silicon diffuses through the electrode in one direction and oxygen diffuses through the electrode in the other direction during the high temperature (400-700.degree. C.) deposition and processing of the dielectric.
摘要翻译：描述了在贵金属硅化物和贵金属之间结合贵金属硅化物，贵金属和富氧阻挡层的层状结构。除了或不含有贵金属硅化物之外，还可以存在硅贡献衬底。本发明克服了制造含有高ε电介质材料的电容器或含有铁电材料的铁电存储元件的问题，即在高温下，硅在一个方向上扩散通过电极，并且氧气在另一个方向扩散通过电极（400-700 电沉积和加工。

10. 发明授权

US5789320A Plating of noble metal electrodes for DRAM and FRAM 失效
标题翻译：电镀DRAM和FRAM的贵金属电极
公开(公告)号：US5789320A
公开(公告)日：1998-08-04
申请号：US636456
申请日：1996-04-23
申请人： Panayotis Constantinou Andricacos , James Hartfiel Comfort , Alfred Grill , David Edward Kotecki , Vishnubhai Vitthalbhai Patel , Katherine Lynn Saenger , Alejandro Gabriel Schrott
发明人： Panayotis Constantinou Andricacos , James Hartfiel Comfort , Alfred Grill , David Edward Kotecki , Vishnubhai Vitthalbhai Patel , Katherine Lynn Saenger , Alejandro Gabriel Schrott
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/44
CPC分类号： H01L27/1085 , H01L28/60
摘要： Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.
摘要翻译：用于DRAM和FRAM的电极的制造中使用预先存在的种子层上的贵金属电镀。电镀可以是空间选择性的或非选择性的。在非选择性情况下，首先将覆盖膜镀覆，然后通过空间选择性材料去除在沉积后进行图案化。在选择性情况下，电镀沉积物可以通过通孔掩模技术在光刻定义的区域中选择性地生长，或者在预先存在的电极结构的暴露区域上选择性地生长为保形涂层。在电镀工艺中可以使用类金刚石碳膜。公开了一种自对准工艺，用于在通过掩模工艺中选择性地涂覆绝缘体。

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