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21. 发明申请

US20080081471A1 TECHNIQUE FOR LOCALLY ADAPTING TRANSISTOR CHARACTERISTICS BY USING ADVANCED LASER/FLASH ANNEAL TECHNIQUES 有权
标题翻译：使用先进激光/闪光技术的局部适应晶体管特性的技术
公开(公告)号：US20080081471A1
公开(公告)日：2008-04-03
申请号：US11736939
申请日：2007-04-18
申请人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
发明人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
IPC分类号： H01L21/44
CPC分类号： H01L21/268 , H01L21/823807 , H01L27/11 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.
摘要翻译：通过对诸如硅化镍之类的金属硅化物形成进行诸如激光退火，闪光退火等复杂的退火技术，可以显着地减少诸如SRAM通孔之类的敏感器件区域中的硅化镍缺陷的风险。此外，可以以高度局部化的方式执行掺杂剂的激活，使得当激活和再结晶漏极和源极区域时，可以避免栅极绝缘层的过度损坏。

22. 发明授权

US06306698B1 Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same 有权
标题翻译：具有栅电极和源/漏区以上的不同厚度的金属硅化物区域的半导体器件及其制造方法
公开(公告)号：US06306698B1
公开(公告)日：2001-10-23
申请号：US09558963
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507
摘要： The present invention is directed to a semiconductor device (100) having enhanced electrical performance characteristics, and a method of making such a device. In one illustrative embodiment, the semiconductor device (100) is comprised of a polysilicon gate electrode (104) positioned above a gate insulation layer (105), a plurality of source/drain regions (109) formed in a semiconducting substrate (101), a first metal silicide region (111A) positioned above the gate electrode (104), a second metal silicide region (107) positioned above each of the source/drain regions (109), wherein the first metal silicide region (111A) is approximately 2-10 times thicker than each of the second metal silicide regions (107). In one illustrative embodiment, the inventive method disclosed herein comprises forming a first layer of a refractory metal (110) above a layer of polysilicon (104), and converting the refractory metal layer (110) to a metal suicide layer (111), and patterning the metal silicide layer (111) and the gate electrode layer (104) to form a metal silicide region (111A) above the gate electrode (104). The method further comprises forming a plurality of source/drain regions (109) in the substrate (101), forming a second layer comprised of a refractory metal above at least the gate stack (122) and the source/drain regions (109). The method concludes with converting at least a portion of the second layer of refractory metal to a second metal silicide region above each of the source/drain regions (109).
摘要翻译：本发明涉及具有增强的电气性能特性的半导体器件（100）以及制造这种器件的方法。在一个说明性实施例中，半导体器件（100）由位于栅极绝缘层（105）上方的多晶硅栅电极（104），形成在半导体衬底（101）中的多个源极/漏极区域（109）位于栅电极（104）上方的第一金属硅化物区（111A），位于源极/漏极区（109）之上的第二金属硅化物区（107），其中第一金属硅化物区（111A）约为2 比第二金属硅化物区域（107）的厚度大10〜10倍。在一个示例性实施例中，本文公开的本发明的方法包括在多晶硅层（104）上方形成难熔金属（110）的第一层，并将难熔金属层（110）转化为金属硅化物层（111），以及图案化金属硅化物层（111）和栅电极层（104）以在栅电极（104）上方形成金属硅化物区域（111A）。该方法还包括在衬底（101）中形成多个源极/漏极区（109），在至少栅极堆叠（122）和源极/漏极区（109）之上形成由难熔金属组成的第二层。该方法的结论是将难熔金属的第二层的至少一部分转换成源极/漏极区域（109）之上的第二金属硅化物区域。

23. 发明授权

US06423634B1 Method of forming low resistance metal silicide region on a gate electrode of a transistor 有权
标题翻译：在晶体管的栅电极上形成低电阻金属硅化物区域的方法
公开(公告)号：US06423634B1
公开(公告)日：2002-07-23
申请号：US09557697
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/66545
摘要： In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and source regions. The protective layer prevents the simultaneous formation of a metal silicide region on the gate electrode. Thereafter, a process layer is formed above the source/drain regions and the cover layer that is positioned above the gate electrode. Next, a surface of the process layer is planarized to expose the cover layer, and the cover layer is removed. Then, a metal silicide region is formed above the gate electrode by depositing a layer of refractory metal and performing at least one anneal process.
摘要翻译：在一个实施例中，在漏极和源极区域上形成低电阻金属硅化物区域之前，在晶体管器件的栅电极的顶表面上形成保护层。保护层防止在栅电极上同时形成金属硅化物区域。此后，在位于栅电极上方的源极/漏极区域和覆盖层之上形成处理层。接下来，将处理层的表面平坦化以露出覆盖层，并且去除覆盖层。然后，通过沉积难熔金属层并进行至少一个退火工艺，在栅电极上方形成金属硅化物区域。

24. 发明授权

US06268257B1 Method of forming a transistor having a low-resistance gate electrode 有权
标题翻译：形成具有低电阻栅电极的晶体管的方法
公开(公告)号：US06268257B1
公开(公告)日：2001-07-31
申请号：US09557714
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/28247 , H01L29/6659
摘要： A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.
摘要翻译：公开了一种方法，其中晶体管的栅电极的低电阻部分形成为独立于在漏极和源极区域中形成低电阻部分。因此，该器件在栅电极中具有厚的低电阻部分，例如，通过最小化栅极电阻来支持低栅极延迟的厚栅极硅化物，以及漏极和源极中的薄的低电阻部分，以便满足浅结合整合的要求。此外，公开了一种具有低电阻栅极电极部分的晶体管，其组成不同于漏极和源极的低电阻部分。

25. 发明授权

US07745334B2 Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniques 有权
标题翻译：通过使用先进的激光/闪光退火技术来局部适应晶体管特性的技术
公开(公告)号：US07745334B2
公开(公告)日：2010-06-29
申请号：US11736939
申请日：2007-04-18
申请人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
发明人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/268 , H01L21/823807 , H01L27/11 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.
摘要翻译：通过对诸如硅化镍之类的金属硅化物形成进行诸如激光退火，闪光退火等复杂的退火技术，可以显着地减少诸如SRAM通孔之类的敏感器件区域中的硅化镍缺陷的风险。此外，可以以高度局部化的方式执行掺杂剂的激活，使得当激活和再结晶漏极和源极区域时，可以避免栅极绝缘层的过度损坏。

26. 发明授权

US06620718B1 Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device 有权
标题翻译：在半导体器件的栅电极和源极/漏极区上形成金属硅化物区域的方法
公开(公告)号：US06620718B1
公开(公告)日：2003-09-16
申请号：US09557713
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L213205
CPC分类号： H01L29/66507 , H01L29/66545
摘要： The present invention is directed to a method of forming metal silicide regions on a gate electrode (23) and on the source/drain regions (25) of a semiconductor device (100). In one illustrative embodiment, the method comprises forming a gate stack (17) above a semiconducting substrate (20), the gate stack (17) being comprised of a gate electrode (23) and a protective layer (24), forming a plurality of source/drain regions (25) in the substrate (20), and forming a first metal silicide region (28) above each of the source/drain regions (25). The method further comprises removing the protective layer (24) from above the gate electrode (23) and forming a second metal silicide region (31) above the gate electrode (23).
摘要翻译：本发明涉及一种在半导体器件（100）的栅电极（23）和源/漏区（25）上形成金属硅化物区的方法。在一个说明性实施例中，该方法包括在半导体衬底（20）上方形成栅极叠层（17），栅叠层（17）由栅电极（23）和保护层（24）组成，形成多个源极/漏极区（25），并且在源极/漏极区（25）之上形成第一金属硅化物区（28）。该方法还包括从栅电极（23）上方去除保护层（24），并在栅电极（23）上方形成第二金属硅化物区域（31）。

27. 发明申请

US20100203698A1 METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译：形成半导体结构的方法
公开(公告)号：US20100203698A1
公开(公告)日：2010-08-12
申请号：US12763324
申请日：2010-04-20
申请人： Frank Wirbeleit , Rolf Stephan , Manfred Horstmann
发明人： Frank Wirbeleit , Rolf Stephan , Manfred Horstmann
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L29/66545 , H01L29/6659
摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.
摘要翻译：形成半导体结构的方法包括提供半导体衬底。在衬底上形成特征。该特征在横向方向上基本上是均匀的。执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。横向的特征长度减小。在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

28. 发明授权

US07629211B2 Field effect transistor and method of forming a field effect transistor 有权
标题翻译：场效应晶体管和形成场效应晶体管的方法
公开(公告)号：US07629211B2
公开(公告)日：2009-12-08
申请号：US11684211
申请日：2007-03-09
申请人： Sven Beyer , Thorsten Kammler , Rolf Stephan , Manfred Horstmann
发明人： Sven Beyer , Thorsten Kammler , Rolf Stephan , Manfred Horstmann
IPC分类号： H01L21/331 , H01L21/8234
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.
摘要翻译：形成场效应晶体管的方法包括提供半导体衬底，栅电极形成在半导体衬底上。在栅电极附近形成至少一个空腔。应变产生元件形成在至少一个空腔中。应变产生元件包括包含第一化学元素和第二化学元素的复合材料。应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比，的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

29. 发明申请

US20080268625A1 ENHANCING TRANSISTOR CHARACTERISTICS BY A LATE DEEP IMPLANTATION IN COMBINATION WITH A DIFFUSION-FREE ANNEAL PROCESS 有权
标题翻译：通过最后深度植入与无扩张的方法进行组合来增强晶体管特性
公开(公告)号：US20080268625A1
公开(公告)日：2008-10-30
申请号：US12023743
申请日：2008-01-31
申请人： Thomas Feudel , Rolf Stephan , Manfred Horstmann
发明人： Thomas Feudel , Rolf Stephan , Manfred Horstmann
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823807 , H01L21/84 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/7843 , H01L29/7848
摘要： By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.
摘要翻译：通过组合用于调节有效沟道长度的退火工艺和在深漏极和源极注入之后执行的基本上无扩散的退火工艺，可以基本上增加漏极和源极区域的垂直延伸，而不影响先前调节的沟道长度。以这种方式，在SOI器件中，漏极和源极区域可以向下延伸到掩埋绝缘层，从而减小寄生电容，同时可以改善延伸区域中的掺杂剂激活程度和因此的串联电阻。此外，在用于调整沟道长度的退火工艺期间较不重要的工艺参数可以为降低晶体管器件的横向尺寸提供潜力。

30. 发明申请

US20080242040A1 METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20080242040A1
公开(公告)日：2008-10-02
申请号：US11942400
申请日：2007-11-19
申请人： Frank Wirbeleit , Rolf Stephan , Manfred Horstmann
发明人： Frank Wirbeleit , Rolf Stephan , Manfred Horstmann
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L29/66545 , H01L29/6659
摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.
摘要翻译：形成半导体结构的方法包括提供半导体衬底。在衬底上形成特征。该特征在横向上基本上是均匀的。执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。横向的特征长度减小。在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

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