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21. 发明授权

US07761687B2 Ultrascalable petaflop parallel supercomputer 失效
标题翻译：超平面petaflop平行超级计算机
公开(公告)号：US07761687B2
公开(公告)日：2010-07-20
申请号：US11768905
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
发明人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
IPC分类号： G06F15/173
CPC分类号： G06F15/17337
摘要： A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.
摘要翻译： petaOPS规模的大规模并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括具有多达四个处理元件的单个专用集成电路（ASIC）。 ASIC节点通过多个独立网络互连，以最小的延迟最大化节点之间的数据包通信的吞吐量。多个网络可以包括用于并行算法消息传递的三个高速网络，包括Torus，集合网络和提供全局障碍和通知功能的全球异步网络。这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。提供DMA引擎的使用以促进节点之间的消息传递，而不需要节点处理资源。

22. 发明申请

US20100138684A1 MEMORY SYSTEM WITH DYNAMIC SUPPLY VOLTAGE SCALING 审中-公开
标题翻译：具有动态电压范围的存储器系统
公开(公告)号：US20100138684A1
公开(公告)日：2010-06-03
申请号：US12326126
申请日：2008-12-02
申请人： Kyu-hyoun Kim , Paul W. Coteus , Alan Gara , Vipin Patel , Kenneth L. Wright
发明人： Kyu-hyoun Kim , Paul W. Coteus , Alan Gara , Vipin Patel , Kenneth L. Wright
IPC分类号： G06F1/04 , G06F1/08
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A memory controller, memory device, and method for dynamic supply voltage scaling in a memory system are provided. The method includes receiving a request for a supply voltage change at the memory controller in the memory system, the supply voltage powering the memory device. The method further includes waiting for any current access of the memory device to complete, and disabling a clock between the memory controller and the memory device. The method also includes changing the supply voltage responsive to the request, and enabling the clock.
摘要翻译：提供了一种存储器控制器，存储器件和用于存储器系统中的动态电源电压缩放的方法。该方法包括在存储器系统中的存储器控制器处接收对电源电压变化的请求，为存储器件提供电源电压。该方法还包括等待存储器设备的任何当前访问以完成存储器控制器和存储器设备之间的时钟的禁用。该方法还包括响应于该请求改变电源电压，并启用时钟。

23. 发明授权

US07668970B2 Optimized scalable network switch 失效
标题翻译：优化可扩展网络交换机
公开(公告)号：US07668970B2
公开(公告)日：2010-02-23
申请号：US11868223
申请日：2007-10-05
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus
IPC分类号： G06F15/173
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2m plurality of compact bit vectors containing information derived from downstream nodes. A multilevel arbitration process in which downstream information stored in the compact vectors, such as link status information and fullness of downstream buffers, is used to determine a preferred direction and virtual channel for packet transmission. Preferred direction ranges are encoded and virtual channels are selected by examining the plurality of compact bit vectors. This dynamic routing method eliminates the necessity of routing tables, thus enhancing scalability of the switch.
摘要翻译：在具有以m多维配置的多个节点的大规模并行计算系统中，每个节点包括计算设备，提供了用于向分组朝向其目的地节点路由分组的方法，其包括生成2m个多个紧凑比特向量中的至少一个包含从下游节点导出的信息。存储在紧凑向量中的下行信息（诸如链路状态信息和下游缓冲器的丰满度）的多级仲裁过程被用于确定分组传输的优选方向和虚拟信道。优选的方向范围被编码，并且通过检查多个紧凑比特向量来选择虚拟信道。这种动态路由方法消除了路由表的必要性，从而增强了交换机的可扩展性。

24. 发明申请

US20100005218A1 ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM 审中-公开
标题翻译：增强的CASCADE互连存储系统
公开(公告)号：US20100005218A1
公开(公告)日：2010-01-07
申请号：US12165816
申请日：2008-07-01
申请人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
发明人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/06
CPC分类号： G06F13/4234
摘要： A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.
摘要翻译：提供了一种用于提供增强级联互连存储器系统的系统，存储器集线器设备，方法和设计结构。该系统包括存储器控制器，存储器通道，耦合到存储器通道的存储器集线器设备，以经由另一个存储器集线器设备的直接连接和级联互连中的一个与存储器控制器进行通信，以及与存储控制器通信的多个存储器设备存储器控制器经由一个或多个级联互连的存储器集线器设备。存储器通道包括耦合到存储器控制器并且可操作用于传输可配置数据帧的单向下游链路段。存储器通道还包括耦合到存储器控制器并且可操作用于传送数据帧的单向上游链路段。

25. 发明申请

US20090201064A1 Phase Interpolator System and Associated Methods 有权
标题翻译：相位插值系统及相关方法
公开(公告)号：US20090201064A1
公开(公告)日：2009-08-13
申请号：US12028973
申请日：2008-02-11
申请人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps , Frank D. Ferrsiolo
发明人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps , Frank D. Ferrsiolo
IPC分类号： H03K3/00
CPC分类号： H03K5/15026 , H03B27/00 , H03H7/21 , H03H11/22 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03K2005/00293
摘要： A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.
摘要翻译：公开了可以包括提供时钟信号的时钟以及与时钟通信以调节时钟信号的强度的控制部分的相位内插器系统。该系统还可以包括发电机电路，以根据从控制部分接收的时钟信号的强度来产生替代时钟信号。

26. 发明申请

US20090161475A1 SYSTEM FOR PROVIDING READ CLOCK SHARING BETWEEN MEMORY DEVICES 失效
标题翻译：用于在存储器件之间提供读取时钟共享的系统
公开(公告)号：US20090161475A1
公开(公告)日：2009-06-25
申请号：US11959711
申请日：2007-12-19
申请人： Kyu-hyoun Kim , Paul W. Coteus
发明人： Kyu-hyoun Kim , Paul W. Coteus
IPC分类号： G11C8/18
CPC分类号： G11C5/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C7/225 , H03L7/07 , H03L7/0812
摘要： A system for providing read clock sharing between memory devices. The system includes a memory device having an external clock receiver, a read clock receiver, and a phase comparator. The phase comparator synchronizes an internal read clock generated at the memory device. The phase comparator additionally synchronizes one of an external clock received by the external clock receiver and an external read clock received by the read clock receiver. The results of the synchronizing are utilized to refresh the internal read clock. The memory device also includes a mechanism, a read clock driver and a mode register fit. The mechanism is utilized to select between the external clock and the external read clock as input to the phase comparator. The read clock driver outputs the internal read clock generated at the memory device to a read clock output pin. The mode register bit controls the selection of the mechanism, the enabling and disabling of the read clock receiver and the enabling and disabling of the read clock driver.
摘要翻译：一种用于在存储器件之间提供读时钟共享的系统。该系统包括具有外部时钟接收器，读取时钟接收器和相位比较器的存储器件。相位比较器同步存储器件产生的内部读时钟。相位比较器还将由外部时钟接收器接收到的外部时钟和由读取时钟接收器接收到的外部读取时钟之一进行同步。利用同步的结果刷新内部读时钟。存储器件还包括机构，读时钟驱动器和模式寄存器配合。该机制用于在外部时钟和外部读取时钟之间选择作为相位比较器的输入。读时钟驱动器将存储器件产生的内部读时钟输出到读时钟输出引脚。模式寄存器位控制机制的选择，读时钟接收器的使能和禁止以及读时钟驱动器的使能和禁止。

27. 发明申请

US20090100664A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 有权
标题翻译：土地网阵列（LGA）利用金属激光器热电偶和其他多点接触几何
公开(公告)号：US20090100664A1
公开(公告)日：2009-04-23
申请号：US12275563
申请日：2008-11-21
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01S4/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. A plurality of slots are formed in the sidewall of said interposer for the venting of gases and pressure therethrough.
摘要翻译：一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触飞机在所述插入器的侧壁中形成多个槽，用于排出气体和通过其中的压力。

28. 发明申请

US20090081891A1 METHOD OF PRODUCING LAND GRID ARRAY (LGA) INTERPOSER GROUPS OF DIFFERENT HEIGHTS UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 失效
标题翻译：使用金属弹性体多角度和其他多点接触几何的不同高度的土地网阵列（LGA）间接组合的方法
公开(公告)号：US20090081891A1
公开(公告)日：2009-03-26
申请号：US12328026
申请日：2008-12-04
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and interposer groupings of different height being mounted on a first surface of said carrier plane. Each interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of each hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
摘要翻译：一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构和不同高度的插入物分组的方法安装在所述载体平面的第一表面上。每个插入件在横截面中具有半环形结构并且由介电弹性体材料构成。多个导电元件围绕每个半环形插入器的表面布置，并且从其最上端向内和向下自由地延伸，与位于电绝缘载体平面相反侧的至少一个部件电接触。

29. 发明申请

US20090049365A1 SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM 有权
标题翻译：用于在存储器系统中提供错误校正和检测的系统和方法
公开(公告)号：US20090049365A1
公开(公告)日：2009-02-19
申请号：US11837785
申请日：2007-08-13
申请人： Kyu-hyoun Kim , Paul W. Coteus , Luis A. Lastras-Montano
发明人： Kyu-hyoun Kim , Paul W. Coteus , Luis A. Lastras-Montano
IPC分类号： G11C29/00 , G06F11/16
CPC分类号： G06F11/1012 , G11C2029/0411
摘要： A system and method for providing error correction and detection in a memory system. The memory system includes a plurality of memory devices, and error detection and correction logic. The error detection and correction logic includes instructions for generating an error correction code (ECC) word that includes bits from two more of the memory devices and from different memory device transfers.
摘要翻译：一种用于在存储器系统中提供纠错和检测的系统和方法。存储器系统包括多个存储器件，以及错误检测和校正逻辑。错误检测和校正逻辑包括用于生成包括来自两个以上存储器设备的位和来自不同存储器件传输的位的纠错码（ECC）字的指令。

30. 发明申请

US20090006683A1 STATIC POWER REDUCTION FOR MIDPOINT-TERMINATED BUSSES 有权
标题翻译：用于中点终端总线的静态功率降低
公开(公告)号：US20090006683A1
公开(公告)日：2009-01-01
申请号：US11768552
申请日：2007-06-26
申请人： Paul W. Coteus , Todd Takken
发明人： Paul W. Coteus , Todd Takken
IPC分类号： G06F13/16
CPC分类号： G06F13/4072 , G06F13/1684 , Y02D10/14 , Y02D10/151
摘要： A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.
摘要翻译：公开了一种存储器系统，其包括存储器控制器和诸如DRAM的可寻址存储器件。本发明提供一种可编程寄存器，以在总线不活动期间控制存储器系统地址和控制总线的每一位的高与低驱动状态。以这种方式，可以使终端电压供应电流最小化，同时允许选择的总线位被驱动到所需状态。这最大限度地减少了终端功耗，同时不影响内存系统的性能。该技术可以扩展到其他高速公交车上。

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