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21. 发明授权

US07682922B2 Post STI trench capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US07682922B2
公开(公告)日：2010-03-23
申请号：US11624385
申请日：2007-01-18
申请人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
IPC分类号： H01L21/20
CPC分类号： H01L29/94 , H01L27/0805 , H01L28/91 , H01L29/66181
摘要： A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成具有用于去耦应用的适当大值的电容器。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

22. 发明授权

US07662722B2 Air gap under on-chip passive device 有权
标题翻译：片下无源器件下的气隙
公开(公告)号：US07662722B2
公开(公告)日：2010-02-16
申请号：US11626548
申请日：2007-01-24
申请人： Anthony K. Stamper , Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , William J. Murphy , Kunal Vaed
发明人： Anthony K. Stamper , Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , William J. Murphy , Kunal Vaed
IPC分类号： H01L21/302
CPC分类号： H01L27/0688 , H01L21/7682 , H01L23/5222 , H01L23/5227 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.
摘要翻译：提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。形成无源器件至少覆盖第一ILD层。使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

23. 发明授权

US07410894B2 Post last wiring level inductor using patterned plate process 失效
标题翻译：使用图案板工艺后最后布线级电感器
公开(公告)号：US07410894B2
公开(公告)日：2008-08-12
申请号：US11161217
申请日：2005-07-27
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John E. Florkey , Jeffrey P. Gambino , Zhong-Xiang He , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John E. Florkey , Jeffrey P. Gambino , Zhong-Xiang He , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L21/44 , H01L21/20 , H01L29/00
CPC分类号： H01L21/76885 , H01L21/76804 , H01L21/76807 , H01L21/76808 , H01L21/76814 , H01L21/76834 , H01L21/76852 , H01L21/76865 , H01L21/76879 , H01L23/5227 , H01L23/53238 , H01L28/10 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.
摘要翻译：一种形成半导体结构的方法以及如此形成的半导体结构，其中诸如电感器的传输线形成在最后一个金属布线层的表面上方的平面上。

24. 发明申请

US20080173918A1 Post STI Trench Capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US20080173918A1
公开(公告)日：2008-07-24
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

25. 发明申请

US20080157382A1 DIRECT TERMINATION OF A WIRING METAL IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中直接终止接线金属
公开(公告)号：US20080157382A1
公开(公告)日：2008-07-03
申请号：US11617202
申请日：2006-12-28
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Ebenezer E. Eshun , Anthony K. Stamper , Richard P. Volant
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Ebenezer E. Eshun , Anthony K. Stamper , Richard P. Volant
IPC分类号： H01L23/48
CPC分类号： H01L23/53223 , H01L23/53228 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/10 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05093 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05568 , H01L2224/05624 , H01L2224/45124 , H01L2224/48724 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Direct termination of a wiring metal in a semiconductor device. Direct termination of an AlCu stack or an AlCu layer is made with an underlying Cu wiring level. The AlCu stack or AlCu layer covers all of the Cu wiring level such that it has a border that extends beyond all of the wiring to prevent exposure from occurring.
摘要翻译：直接终止半导体器件中的布线金属。 AlCu堆叠或AlCu层的直接终止是用下面的铜布线层进行的。 AlCu堆叠或AlCu层覆盖所有Cu布线级别，使得其具有延伸超出所有布线的边界，以防止发生曝光。

26. 发明申请

US20080157270A1 Metal to Metal Low-K Antifuse 审中-公开
标题翻译：金属与金属Low-K防腐剂
公开(公告)号：US20080157270A1
公开(公告)日：2008-07-03
申请号：US11618757
申请日：2006-12-30
申请人： Deok-kee Kim , Anil K. Chinthakindi , Son Van Nguyen , Kelly Malone , Byeongju Park
发明人： Deok-kee Kim , Anil K. Chinthakindi , Son Van Nguyen , Kelly Malone , Byeongju Park
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of the invention generally relate to fuse and anti-fuse structures and include a copper conductor positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that an antifuse element region of the dielectric is positioned between the resistor and the metal cap. The antifuse element region of the dielectric is adapted to change resistance values by application of a voltage difference between the resistor and the copper conductor/metal cap. The antifuse element region has a first higher resistance (more closely matching an insulator) before application of the voltage and a second lower resistance (more closely matching a conductor) after application of such voltage. In one embodiment herein the voltage can be supplemented by heating through application of voltage through the first conductor which helps change the resistance of the antifuse element region.
摘要翻译：本发明的实施例一般涉及熔丝和反熔丝结构，并且包括定位在基板内的铜导体和第一导体上的金属盖。低k电介质位于基板和金属盖上。电介质上的氮化钽电阻器，电阻器位于金属帽的上方，使得电介质的反熔丝元件区域位于电阻器和金属帽之间。电介质的反熔丝元件区域适于通过施加电阻器和铜导体/金属帽之间的电压差来改变电阻值。在施加电压之后，反熔丝元件区域具有第一高电阻（更紧密地匹配绝缘体）和施加电压之后的第二较低电阻（更接近地匹配导体）。在本文的一个实施例中，可以通过施加通过第一导体的电压进行加热来补充电压，这有助于改变反熔丝元件区域的电阻。

27. 发明申请

US20080130200A1 Integrated Circuit Comb Capacitor 有权
标题翻译：集成电路梳状电容器
公开(公告)号：US20080130200A1
公开(公告)日：2008-06-05
申请号：US12034728
申请日：2008-02-21
申请人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
发明人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
IPC分类号： H01G4/38
CPC分类号： H01L23/5223 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
摘要翻译：本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

28. 发明申请

US20070284662A1 MICROELECTRONIC STRUCTURE INCLUDING HIGH CURRENT DENSITY RESISTOR 审中-公开
标题翻译：微电子结构包括高电流密度电阻
公开(公告)号：US20070284662A1
公开(公告)日：2007-12-13
申请号：US11423232
申请日：2006-06-09
申请人： Anil K. Chinthakindi , Baozhen Li , Gerald R. Matusiewicz
发明人： Anil K. Chinthakindi , Baozhen Li , Gerald R. Matusiewicz
IPC分类号： H01L27/12
CPC分类号： H01L27/0629 , H01L28/20
摘要： A microelectronic structure and a method for fabricating the microelectronic structure include a resistor located and formed over a substrate. A conductor contact layer contacts the resistor. A maximum length of the conductor contact layer is determined using a Blech constant to avoid electromigration of a conductor material that comprises the conductor contact layer.
摘要翻译：微电子结构和用于制造微电子结构的方法包括位于衬底上并形成的电阻器。导体接触层接触电阻。使用Blech常数确定导体接触层的最大长度，以避免包含导体接触层的导体材料的电迁移。

29. 发明授权

US07265019B2 Elastomeric CMOS based micro electromechanical varactor 有权
标题翻译：弹性体CMOS微机电变容二极管
公开(公告)号：US07265019B2
公开(公告)日：2007-09-04
申请号：US10710286
申请日：2004-06-30
申请人： Anil K. Chinthakindi , Henri D. Schnurmann
发明人： Anil K. Chinthakindi , Henri D. Schnurmann
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01G5/18 , H01G5/38
摘要： A micro electro-mechanical system (MEMS) variable capacitor is described, wherein movable comb electrodes of opposing polarity are fabricated simultaneously on the same substrate and are independently actuated. The electrodes are formed in an interdigitated fashion to maximize capacitance. The MEMS variable capacitor includes CMOS manufacturing steps in combination with elastomeric material selectively used in areas under greatest stress to ensure that the varactor will not fail as a result of stresses that may result in the separation of dielectric material from the conductive elements. The combination of a CMOS process with the conducting elastomeric material between vias increases the overall sidewall area, which provides increased capacitance density.
摘要翻译：描述了微机电系统（MEMS）可变电容器，其中相同极性的可移动梳状电极同时制造在相同的衬底上并且被独立地致动。电极以交叉形式形成以最大化电容。 MEMS可变电容器包括与在最大应力区域选择性地使用的弹性体材料组合的CMOS制造步骤，以确保变容二极管不会由于可能导致介电材料与导电元件分离的应力而失效。 CMOS工艺与通孔之间的导电弹性体材料的组合增加了整个侧壁面积，这提供了增加的电容密度。

30. 发明授权

US07166913B2 Heat dissipation for heat generating element of semiconductor device and related method 有权
标题翻译：半导体器件发热元件的散热及相关方法
公开(公告)号：US07166913B2
公开(公告)日：2007-01-23
申请号：US10907873
申请日：2005-04-19
申请人： Anil K. Chinthakindi , Lawrence A. Clevenger , Tom C. Lee , Gerald Matusiewicz , Conal E. Murray , Chih-Chao Yang
发明人： Anil K. Chinthakindi , Lawrence A. Clevenger , Tom C. Lee , Gerald Matusiewicz , Conal E. Murray , Chih-Chao Yang
IPC分类号： H01L23/34
CPC分类号： H01L23/5228 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.
摘要翻译：公开了相对于半导体器件中的发热元件的散热的结构和方法。该结构包括多个与发热元件垂直一致的传热线，以及从每个传热线到半导体器件的基板的至少一个互连路径。在一个实施例中，发热元件包括非第一金属水平的电阻器。本发明与传统的BEOL互连方案兼容，使得从电阻器到周围互连布线的传热量最小化，从而消除了布线中的载流能力的损失。

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