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21. 发明申请

US20060095722A1 Program subgraph identification 有权
标题翻译：程序子图识别
公开(公告)号：US20060095722A1
公开(公告)日：2006-05-04
申请号：US11048663
申请日：2005-01-31
申请人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/00
CPC分类号： G06F8/4441
摘要： There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing logic operable to execute respective separate program instructions from said program; and accelerator logic operable in response to reaching an execution point within said program associated with a subgraph suggestion to execute a sequence of program instructions corresponding to said subgraph suggestion as an accelerated operation instead of executing said sequence of program instructions as respective separate program instructions with said processing logic.
摘要翻译：提供了一种用于在具有程序指令和子图建议信息的程序的控制下处理数据的装置，该子图表建议信息识别与所述程序中识别的计算子图相对应的程序指令的相应序列，所述装置包括：存储器，可操作以存储由单独程序形成的程序说明书处理逻辑可操作以从所述程序执行相应的单独的程序指令; 以及加速器逻辑，其可操作以响应于到达与子图建议相关联的所述程序内的执行点，以执行对应于所述子图建议的程序指令序列作为加速操作，而不是执行所述程序指令序列作为具有所述处理逻辑。

22. 发明申请

US20050022094A1 Systematic and random error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内的系统和随机的错误检测和恢复
公开(公告)号：US20050022094A1
公开(公告)日：2005-01-27
申请号：US10896997
申请日：2004-07-23
申请人： Trevor Mudge , Todd Austin , David Blaauw , Krisztian Flautner
发明人： Trevor Mudge , Todd Austin , David Blaauw , Krisztian Flautner
IPC分类号： G06F11/10 , G06F11/16 , G06F9/30 , G06F9/40 , G06F15/00 , H03M13/00
CPC分类号： G06F11/1695 , G06F9/3861 , G06F9/3869 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

23. 发明授权

US08650470B2 Error recovery within integrated circuit 有权
标题翻译：集成电路内的错误恢复
公开(公告)号：US08650470B2
公开(公告)日：2014-02-11
申请号：US12926084
申请日：2010-10-25
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/00 , G06F11/0706 , G06F11/0736 , G06F11/0754 , G06F11/0757 , G06F11/079 , G06F11/1402 , G06F11/1604
摘要： An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.
摘要翻译：集成电路包括具有错误检测和误差校正电路的一个或多个部分，并且其操作参数给出有限的非零误码率以及形成和操作以提供零错误率的一个或多个部分。

24. 发明授权

US08407537B2 Error recover within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内发生错误恢复
公开(公告)号：US08407537B2
公开(公告)日：2013-03-26
申请号：US12923908
申请日：2010-10-13
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F1/08 , G06F11/30
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

25. 发明申请

US20110126051A1 Error recover within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内发生错误恢复
公开(公告)号：US20110126051A1
公开(公告)日：2011-05-26
申请号：US12923908
申请日：2010-10-13
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F11/267
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

26. 发明授权

US07769982B2 Data processing apparatus and method for accelerating execution of subgraphs 有权
标题翻译：用于加速执行子图的数据处理装置和方法
公开(公告)号：US07769982B2
公开(公告)日：2010-08-03
申请号：US11884362
申请日：2005-06-22
申请人： Sami Yehia , Krisztian Flautner
发明人： Sami Yehia , Krisztian Flautner
IPC分类号： G06F9/38 , G06F9/318
CPC分类号： G06F9/3885 , G06F9/30181 , G06F9/3877
摘要： A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph. The evaluation of each output function generates an output operand for storing in the operand store, and each output operand corresponds to an output that would have been generated had the sequence of individual program instructions corresponding to the computational subgraph have been executed by the processing logic. Configuration storage stores a single look-up table (LUT) configuration for each output function, and for each output function to be evaluated, the accelerator logic is configured dependent on the associated single LUT configuration from the configuration storage, such that on receipt of the input operands of the computational subgraph, the accelerator logic will generate the output operand. This technique has been found to provide a particularly efficient accelerator logic for evaluating output functions associated with computational subgraphs.
摘要翻译：提供了一种数据处理装置和方法，用于在具有程序指令的程序的控制下处理数据，该程序指令包括与程序内识别的计算子图相对应的各个程序指令的序列。每个计算子图具有多个输入操作数，并产生一个或多个输出操作数。该装置包括用于存储输入和输出操作数的操作数存储器和用于从程序执行各个程序指令的处理逻辑。还提供了可配置加速器逻辑，其响应于到达程序内的执行点，对应于与计算子图对应的单独程序指令的序列，来评估与计算子图相关联的一个或多个输出函数。每个输出函数的评估产生用于存储在操作数存储中的输出操作数，并且每个输出操作数对应于如果已经由处理逻辑执行了与计算子图对应的单个程序指令的序列，则该输出将被产生。配置存储器存储用于每个输出功能的单个查找表（LUT）配置，并且对于要评估的每个输出功能，加速器逻辑被配置为取决于来自配置存储器的相关联的单个LUT配置，使得在接收到输入操作数的计算子图，加速器逻辑将产生输出操作数。已经发现这种技术提供了用于评估与计算子图相关联的输出函数的特别有效的加速器逻辑。

27. 发明申请

US20090213673A1 Data processor memory circuit 审中-公开
公开(公告)号：US20090213673A1
公开(公告)日：2009-08-27
申请号：US12382450
申请日：2009-03-17
申请人： Krisztian Flautner , David T. Blaauw , Trevo N. Mudge , Nam S. Kim , Steven M. Martin
发明人： Krisztian Flautner , David T. Blaauw , Trevo N. Mudge , Nam S. Kim , Steven M. Martin
IPC分类号： G11C7/00 , G11C5/14 , G11C8/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

28. 发明申请

US20070239969A1 Program subgraph identification 有权
标题翻译：程序子图识别
公开(公告)号：US20070239969A1
公开(公告)日：2007-10-11
申请号：US11806907
申请日：2007-06-05
申请人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F9/305
CPC分类号： G06F8/4441
摘要： There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing logic operable to execute respective separate program instructions from said program; and accelerator logic operable in response to reaching an execution point within said program associated with a subgraph suggestion to execute a sequence of program instructions corresponding to said subgraph suggestion as an accelerated operation instead of executing said sequence of program instructions as respective separate program instructions with said processing logic.
摘要翻译：提供了一种用于在具有程序指令和子图建议信息的程序的控制下处理数据的装置，该子图表建议信息识别与所述程序中识别的计算子图相对应的程序指令的相应序列，所述装置包括：存储器，可操作以存储由单独程序形成的程序说明书处理逻辑可操作以从所述程序执行相应的单独的程序指令; 以及加速器逻辑，其可操作以响应于到达与子图建议相关联的所述程序内的执行点，以执行对应于所述子图建议的程序指令序列作为加速操作，而不是执行所述程序指令序列作为具有所述处理逻辑。

29. 发明授权

US07278080B2 Error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：集成电路处理阶段内的错误检测和恢复
公开(公告)号：US07278080B2
公开(公告)日：2007-10-02
申请号：US10392382
申请日：2003-03-20
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F11/10
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a maimer that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑2，非延迟锁存器4，延迟锁存器8和比较器6。非延迟锁存器4在非延迟捕获时间捕获来自处理逻辑2的输出。在稍后的延迟捕获时间，延迟锁存器8也捕获来自处理逻辑2的值。比较器6比较这些值，如果它们不相等，则表示非延迟值被捕获得太早，应该被延迟值代替。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便在增加整体性能的情况下保持有限的非零错误率。

30. 发明授权

US07162661B2 Systematic and random error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内的系统和随机的错误检测和恢复
公开(公告)号：US07162661B2
公开(公告)日：2007-01-09
申请号：US10779805
申请日：2004-02-18
申请人： Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Krisztian Flautner
发明人： Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Krisztian Flautner
IPC分类号： G06F11/10
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024。非延迟信号捕获元件1016在非延迟捕获时间捕获来自处理逻辑1014的输出。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。误差检测电路1026和误差校正电路1028检测并校正延迟值中的随机误差，并将错误检测的延迟值提供给比较器1024。比较器1024比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获得太早，应该被错误检查的延迟值替换。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

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