专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060095722A1 Program subgraph identification 有权
标题翻译：程序子图识别
公开(公告)号：US20060095722A1
公开(公告)日：2006-05-04
申请号：US11048663
申请日：2005-01-31
申请人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/00
CPC分类号： G06F8/4441
摘要： There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing logic operable to execute respective separate program instructions from said program; and accelerator logic operable in response to reaching an execution point within said program associated with a subgraph suggestion to execute a sequence of program instructions corresponding to said subgraph suggestion as an accelerated operation instead of executing said sequence of program instructions as respective separate program instructions with said processing logic.
摘要翻译：提供了一种用于在具有程序指令和子图建议信息的程序的控制下处理数据的装置，该子图表建议信息识别与所述程序中识别的计算子图相对应的程序指令的相应序列，所述装置包括：存储器，可操作以存储由单独程序形成的程序说明书处理逻辑可操作以从所述程序执行相应的单独的程序指令; 以及加速器逻辑，其可操作以响应于到达与子图建议相关联的所述程序内的执行点，以执行对应于所述子图建议的程序指令序列作为加速操作，而不是执行所述程序指令序列作为具有所述处理逻辑。

2. 发明申请

US20070239969A1 Program subgraph identification 有权
标题翻译：程序子图识别
公开(公告)号：US20070239969A1
公开(公告)日：2007-10-11
申请号：US11806907
申请日：2007-06-05
申请人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F9/305
CPC分类号： G06F8/4441
摘要： There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing logic operable to execute respective separate program instructions from said program; and accelerator logic operable in response to reaching an execution point within said program associated with a subgraph suggestion to execute a sequence of program instructions corresponding to said subgraph suggestion as an accelerated operation instead of executing said sequence of program instructions as respective separate program instructions with said processing logic.
摘要翻译：提供了一种用于在具有程序指令和子图建议信息的程序的控制下处理数据的装置，该子图表建议信息识别与所述程序中识别的计算子图相对应的程序指令的相应序列，所述装置包括：存储器，可操作以存储由单独程序形成的程序说明书处理逻辑可操作以从所述程序执行相应的单独的程序指令; 以及加速器逻辑，其可操作以响应于到达与子图建议相关联的所述程序内的执行点，以执行对应于所述子图建议的程序指令序列作为加速操作，而不是执行所述程序指令序列作为具有所述处理逻辑。

3. 发明申请

US20060095721A1 Tightly coupled accelerator 有权
标题翻译：紧耦合加速器
公开(公告)号：US20060095721A1
公开(公告)日：2006-05-04
申请号：US11046555
申请日：2005-01-31
申请人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F8/44 , G06F9/3005 , G06F9/30054 , G06F9/3806 , G06F9/3836 , G06F9/3897
摘要： An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.
摘要翻译：加速器120紧密耦合到正常执行单元110。执行单元和加速器单元共享作为寄存器文件130的操作数存储器，基于栈的操作数存储或其他操作数存储。操作数也可以在指令本身内作为立即值访问。与计算子图相对应的单独程序指令的顺序保持在程序内，但是可被加速器识别为适合于加速，并且当遇到由加速器而不是由正常执行单元执行时。在这种紧密耦合的布置中，由于系统内缺少寄存器资源，可能会出现问题。本技术提供了在加速器内生成但被确定不被引用到有关的计算子图之外的至少一些中间操作数值不被写入操作数存储。

4. 发明申请

US20060095720A1 Reuseable configuration data 有权
标题翻译：可重复使用的配置数据
公开(公告)号：US20060095720A1
公开(公告)日：2006-05-04
申请号：US11044734
申请日：2005-01-28
申请人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F8/433 , G06F8/44 , G06F9/30043 , G06F9/3005 , G06F9/30054 , G06F9/3017 , G06F9/30174 , G06F9/3806 , G06F9/3897
摘要： There is provided an information processor for executing a program comprising a plurality of separate program instructions: processing logic operable to individually execute said separate program instructions of said program; an operand store operable to store operand values; and an accelerator having an array comprising a plurality of functional units, said accelerator being operable to execute a combined operation corresponding to a computational subgraph of said separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with one or more processing stages of said combined operation; wherein said accelerator executes said combined operation in dependence upon operand mapping data providing a mapping between operands of said combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between said plurality of functional units and said particular processing operations such that said configuration data can be re-used for different operand mappings.
摘要翻译：提供了一种用于执行程序的信息处理器，该程序包括多个单独的程序指令：可操作以单独执行所述程序的所述单独的程序指令的处理逻辑; 可操作地存储操作数值的操作数存储器; 以及具有包括多个功能单元的阵列的加速器，所述加速器可操作以通过配置所述多个功能单元中的各个功能单元执行与一个功能单元相关联的特定处理操作来执行对应于所述单独程序指令的计算子图的组合操作或更多的处理阶段; 其中所述加速器根据操作数映射数据执行所述组合操作，所述操作数映射数据提供所述组合操作的操作数与所述操作数存储之间的存储位置之间的映射，并且依赖于提供所述多个功能单元之间的映射和所述特定处理使得所述配置数据可以被重新用于不同的操作数映射的操作。

5. 发明授权

US07343482B2 Program subgraph identification 有权
标题翻译：程序子图识别
公开(公告)号：US07343482B2
公开(公告)日：2008-03-11
申请号：US11048663
申请日：2005-01-31
申请人： Stuart David Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart David Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F9/00
CPC分类号： G06F8/4441
摘要： There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing logic operable to execute respective separate program instructions from said program; and accelerator logic operable in response to reaching an execution point within said program associated with a subgraph suggestion to execute a sequence of program instructions corresponding to said subgraph suggestion as an accelerated operation instead of executing said sequence of program instructions as respective separate program instructions with said processing logic.
摘要翻译：提供了一种用于在具有程序指令和子图建议信息的程序的控制下处理数据的装置，该子图表建议信息识别与所述程序中识别的计算子图相对应的程序指令的相应序列，所述装置包括：存储器，可操作以存储由单独程序形成的程序说明书处理逻辑可操作以从所述程序执行相应的单独的程序指令; 以及加速器逻辑，其可操作以响应于到达与子图建议相关联的所述程序内的执行点，以执行对应于所述子图建议的程序指令序列作为加速操作，而不是执行所述程序指令序列作为具有所述处理逻辑。

6. 发明授权

US08505002B2 Translation of SIMD instructions in a data processing system 有权
标题翻译： SIMD指令在数据处理系统中的翻译
公开(公告)号：US08505002B2
公开(公告)日：2013-08-06
申请号：US11905160
申请日：2007-09-27
申请人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
发明人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
IPC分类号： G06F9/45
CPC分类号： G06F9/30054 , G06F9/30032 , G06F9/30036 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3885 , G06F9/3887 , G06F9/45516
摘要： A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.
摘要翻译：提供了一种数据处理系统，其具有处理器和分析电路，用于识别与第一SIMD指令集相关联的SIMD指令，并通过功能等效的标量表示代替它并标记该功能等效的标量表示。标记的功能等效标量表示在执行程序时使用转换电路进行动态转换，以生成对应于与所识别的SIMD指令相对应的第一SIMD架构不同的指令集架构的一个或多个相应的转换指令。

7. 发明申请

US20080141012A1 Translation of SIMD instructions in a data processing system 有权
标题翻译： SIMD指令在数据处理系统中的翻译
公开(公告)号：US20080141012A1
公开(公告)日：2008-06-12
申请号：US11905160
申请日：2007-09-27
申请人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
发明人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
IPC分类号： G06F9/318
CPC分类号： G06F9/30054 , G06F9/30032 , G06F9/30036 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3885 , G06F9/3887 , G06F9/45516
摘要： A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.
摘要翻译：提供了一种数据处理系统，其具有处理器和分析电路，用于识别与第一SIMD指令集相关联的SIMD指令，并通过功能等效的标量表示代替它并标记该功能等效的标量表示。标记的功能等效标量表示在执行程序时使用转换电路进行动态转换，以生成对应于与所识别的SIMD指令相对应的第一SIMD架构不同的指令集架构的一个或多个相应的转换指令。

8. 发明授权

US07318143B2 Reuseable configuration data 有权
标题翻译：可重复使用的配置数据
公开(公告)号：US07318143B2
公开(公告)日：2008-01-08
申请号：US11044734
申请日：2005-01-28
申请人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/80
CPC分类号： G06F9/3885 , G06F8/433 , G06F8/44 , G06F9/30043 , G06F9/3005 , G06F9/30054 , G06F9/3017 , G06F9/30174 , G06F9/3806 , G06F9/3897
摘要： An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store operable to store operand values and an accelerator having a plurality of functional units. The accelerator executes a combined operation corresponding to a computational sub-graph of the separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with the combined operation. The accelerator executes the combined operation in dependence upon operand mapping data providing a mapping between operands of the combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between the plurality of functional units and the particular processing operations. The configuration data can be re-used for different operand mappings.
摘要翻译：提供了一种用于执行包括多个独立程序指令的程序的信息处理器。处理器包括可操作以单独执行所述程序的所述单独程序指令的处理逻辑，可操作以存储操作数值的操作数存储器和具有多个功能单元的加速器。加速器通过将所述多个功能单元中的各个功能单元配置为执行与组合操作相关联的特定处理操作，执行与单独程序指令的计算子图相对应的组合操作。加速器根据操作数映射数据执行组合操作，该数据提供组合操作的操作数与所述操作数存储之间的存储位置之间的映射，并且依赖于提供多个功能单元与特定处理操作之间的映射的单独指定的配置数据。配置数据可以重新用于不同的操作数映射。

9. 发明授权

US07685404B2 Program subgraph identification 有权
标题翻译：程序子图识别
公开(公告)号：US07685404B2
公开(公告)日：2010-03-23
申请号：US11806907
申请日：2007-06-05
申请人： Stuart David Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart David Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F9/00
CPC分类号： G06F8/4441
摘要： An apparatus is provided for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within the program. A memory stores a program formed of separate program instructions. Processing logic executes respective separate program instructions from said program. Accelerator logic, in response to reaching an execution point within the program associated with a subgraph suggestion, executes a sequence of program instructions corresponding to the subgraph suggestion as an accelerated operation instead of executing the sequence of program instructions as respective separate program instructions with the processing logic.
摘要翻译：提供了一种用于在具有程序指令和子图表建议信息的程序的控制下处理数据的装置，其识别与程序内识别的计算子图相对应的程序指令的各个序列。存储器存储由单独的程序指令形成的程序。处理逻辑从所述程序执行相应的单独的程序指令。加速器逻辑响应于到达与子图建议相关联的程序中的执行点，执行对应于子图建议的程序指令序列作为加速操作，而不是执行程序指令序列作为相应的单独的程序指令，其中处理逻辑。

10. 发明授权

US07350055B2 Tightly coupled accelerator 有权
标题翻译：紧耦合加速器
公开(公告)号：US07350055B2
公开(公告)日：2008-03-25
申请号：US11046555
申请日：2005-01-31
申请人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/16
CPC分类号： G06F9/3885 , G06F8/44 , G06F9/3005 , G06F9/30054 , G06F9/3806 , G06F9/3836 , G06F9/3897
摘要： An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.
摘要翻译：加速器120紧密耦合到正常执行单元110。执行单元和加速器单元共享作为寄存器文件130的操作数存储器，基于栈的操作数存储或其他操作数存储。操作数也可以在指令本身内作为立即值访问。与计算子图相对应的单独程序指令的顺序保持在程序内，但是可被加速器识别为适合于加速，并且当遇到由加速器而不是由正常执行单元执行时。在这种紧密耦合的布置中，由于系统内缺少寄存器资源，可能会出现问题。本技术规定，在加速器内产生但被确定为不被引用在有关的计算子图之外的至少一些中间操作数值不被写入操作数存储。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式