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21. 发明授权

US5227269A Method for fabricating high density DRAM reticles 失效
标题翻译：制造高密度DRAM掩模版的方法
公开(公告)号：US5227269A
公开(公告)日：1993-07-13
申请号：US542293
申请日：1990-06-22
申请人： David B. Scott
发明人： David B. Scott
IPC分类号： G03F7/20
CPC分类号： G03F7/70425 , G03F7/70433 , G03F7/70458
摘要： A method of reticle fabrication is disclosed which will reduce e-beam write time by two orders of magnitude for a 64 megabit DRAM. The method involves the mix of using both e-beam and optical lithography on a single reticle.
摘要翻译：公开了一种掩模版制造的方法，其将64兆比特DRAM的电子束写入时间减少两个数量级。该方法涉及在单个掩模版上使用电子束和光学光刻的混合。

22. 发明授权

US4754314A Split-level CMOS 失效
标题翻译：分体式CMOS
公开(公告)号：US4754314A
公开(公告)日：1988-06-28
申请号：US9004
申请日：1987-01-28
申请人： David B. Scott , Satwinder S. Malhi
发明人： David B. Scott , Satwinder S. Malhi
IPC分类号： H01L21/822 , H01L27/06 , H01L27/092 , H01L27/02 , H01L29/04 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221 , H01L27/0922
摘要： A CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.
摘要翻译： CMOS器件，其中NMOS器件是体器件，PMOS器件是SOI器件。 PMOS器件在绝缘体上硅层中形成它们的沟道区，优选在二氧化硅层上形成横向再结晶的退火多晶硅层。

23. 发明授权

US08768520B2 Systems and methods for controlling a bedroom environment and for providing sleep data 有权
标题翻译：用于控制卧室环境和提供睡眠数据的系统和方法
公开(公告)号：US08768520B2
公开(公告)日：2014-07-01
申请号：US12919189
申请日：2008-11-14
申请人： Robert D. Oexman , David B. Scott
发明人： Robert D. Oexman , David B. Scott
IPC分类号： G06F19/00
CPC分类号： A61M21/02 , A47C27/061 , A47C27/082 , A47C27/083 , A47C27/10 , A47C27/18 , A47C31/123 , A61G7/05769 , A61G2203/34 , A61M16/161 , A61M2021/0027 , A61M2021/0044 , A61M2021/0066 , A61M2205/332 , A61M2205/3368 , A61M2205/3375 , A61M2205/3553 , A61M2205/3584 , A61M2205/3592 , A61M2205/502 , A61M2205/52 , A61M2230/06 , A61M2230/42 , A61M2230/50 , A61M2230/62 , A61M2230/63 , F24F3/14 , F24F11/0001 , F24F11/30 , F24F11/66 , G06F19/00 , A61M2230/005
摘要： A system for controlling a bedroom environment includes an environmental data collector configured to collect environmental data relating to the bedroom environment; a sleep data collector configured to collect sleep data relating to a person's state of sleep; an analysis unit configured to analyze the collected environmental data and the collected sleep data and to determine an adjustment of the bedroom environment that promotes sleep of the person; and a controller configured to effect the adjustment of the bedroom environment. A method for controlling a bedroom environment includes collecting environmental data relating to the bedroom environment; collecting sleep data relating to a person's state of sleep; analyzing the collected environmental data and the collected sleep data; determining an adjustment to the bedroom environment that promotes sleep; and communicating the adjustment to a device that effects the bedroom environment.
摘要翻译：一种用于控制卧室环境的系统包括：环境数据收集器，被配置为收集与卧室环境相关的环境数据; 配置为收集与人的睡眠状态有关的睡眠数据的睡眠数据收集器; 分析单元，其被配置为分析所收集的环境数据和收集的睡眠数据，并且确定促进人的睡眠的卧室环境的调整; 以及控制器，被配置为实现卧室环境的调节。一种用于控制卧室环境的方法包括收集与卧室环境相关的环境数据; 收集与一个人的睡眠状态有关的睡眠数据; 分析收集的环境数据和收集的睡眠数据; 确定对促进睡眠的卧室环境的调整; 并将该调整传达给影响卧室环境的装置。

24. 发明申请

US20100317930A1 APPARATUSES AND METHODS FOR EVALUATING A PERSON FOR A SLEEP SYSTEM 有权
标题翻译：评估睡眠系统人员的方法和方法
公开(公告)号：US20100317930A1
公开(公告)日：2010-12-16
申请号：US12867740
申请日：2008-11-14
申请人： Robert D. Oexman , David B. Scott
发明人： Robert D. Oexman , David B. Scott
IPC分类号： A61B5/00
CPC分类号： A47C31/123
摘要： A method for evaluating a person for a sleep system, the method including: while the person is not positioned on an evaluating member, adjusting a pressure of a comfort layer inflatable member disposed within a comfort layer of the evaluating member to an initial comfort value; positioning the person on the evaluating member in a first position; while the person is positioned on the evaluating member in the first position, measuring a pressure of the comfort layer inflatable member as a first measured comfort value; calculating a difference between the first measured comfort value and the initial comfort value as comfort pressure 1; calculating a first optimal pressure level for the comfort layer inflatable member using comfort pressure 1; and recommending a sleep support member for the person using the calculated first optimal pressure level for the comfort layer inflatable member and using data measuring quality of sleep.
摘要翻译：一种用于评估睡眠系统的人的方法，所述方法包括：当所述人不位于评估构件上时，将设置在所述评估构件的舒适层内的舒适层可充气构件的压力调节到初始舒适值; 将人员放置在评估构件的第一位置; 当所述人在所述第一位置处定位在所述评估构件上时，测量所述舒适层可充气构件的压力作为第一测量舒适度值; 计算第一测量舒适度值和初始舒适度值之间的差作为舒适压力1; 使用舒适压力1计算舒适层可充气构件的第一最佳压力水平; 并且使用所计算的用于舒适层可充气构件的第一最佳压力水平并使用测量睡眠质量的数据来为人推荐睡眠支撑构件。

25. 发明申请

US20100313359A1 APPARATUSES AND METHODS FOR AUTOMATIC PILLOW ADJUSTMENT 有权
标题翻译：自动枕式调整的装置和方法
公开(公告)号：US20100313359A1
公开(公告)日：2010-12-16
申请号：US12867684
申请日：2009-02-13
申请人： David B. Scott , Robert D. Oexman
发明人： David B. Scott , Robert D. Oexman
IPC分类号： A47G9/10
CPC分类号： A47G9/1027
摘要： An adjustable head support apparatus includes an adjustable head support member including one or more inflatable members; and an encasement layer configured to encase the one or more inflatable members. The adjustable head support apparatus further includes a measurement unit configured to provide measurements relating to a pressure of the one or more inflatable members; an analysis unit configured to determine goal characteristics of the adjustable head support member for a person using the measurements relating to the pressure of the one or more inflatable members; and a control unit configured to control adjustments to pressure of the one or more inflatable members using the determined goal characteristics.
摘要翻译：一种可调节的头部支撑装置，包括一个包括一个或多个可膨胀构件的可调头部支撑构件; 以及被配置为包住所述一个或多个可充气构件的包围层。可调节头部支撑装置还包括测量单元，其被配置为提供与一个或多个可充气构件的压力有关的测量; 分析单元，其被配置为使用与所述一个或多个可充气构件的压力相关的测量值来确定人的可调节头部支撑构件的目标特性; 以及控制单元，其被配置为使用所确定的目标特性来控制对所述一个或多个可充气构件的压力的调节。

26. 发明授权

US07639056B2 Ultra low area overhead retention flip-flop for power-down applications 有权
标题翻译：用于断电应用的超低面积开销保持触发器
公开(公告)号：US07639056B2
公开(公告)日：2009-12-29
申请号：US11138788
申请日：2005-05-26
申请人： Sumanth Katte Gururajarao , Hugh T. Mair , David B. Scott , Uming Ko
发明人： Sumanth Katte Gururajarao , Hugh T. Mair , David B. Scott , Uming Ko
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356008 , H04W52/0283 , Y02D70/122
摘要： In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.
摘要翻译：在用于数据保持的方法和系统中，数据输入由第一锁存器锁存。耦合到第一锁存器的第二锁存器接收用于保持的数据输入，而在备用电源模式下第一锁存器不工作。第一个锁存器在待机电源模式期间从关闭的第一电源线接收电力。第二锁存器从第二电源线接收电力。控制器接收时钟输入和保持信号，并向第一锁存器和第二锁存器提供时钟输出。保持信号的改变表示转变到待机功率模式。控制器继续将时钟输出保持在预定的电压电平，并且第二锁存器在待机功率模式下继续从第二电源线接收电力，从而保留数据输入。

27. 发明授权

US07164291B2 Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors 有权
标题翻译：具有低泄漏PMOS和高泄漏NMOS晶体管的集成标头开关
公开(公告)号：US07164291B2
公开(公告)日：2007-01-16
申请号：US10916135
申请日：2004-08-11
申请人： Hugh T. Mair , David B. Scott , Rolf Lagerquist
发明人： Hugh T. Mair , David B. Scott , Rolf Lagerquist
IPC分类号： H03K19/0175 , G05F1/10
CPC分类号： H03K17/6872 , H03K19/0013 , H03K19/00315 , H03K2217/0036
摘要： System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.
摘要翻译：为集成电路中的电路提供大的导通电流和小的截止电流的系统和方法。优选实施例包括用于向由PMOS晶体管和并联的NMOS晶体管制成的集成电路中的电路提供功率的开关。每个晶体管的栅极端子耦合到单独的控制信号线。 PMOS晶体管以高电压电源电平向电路提供电流，而NMOS晶体管以低电压电源电平向电路提供电流，其中可以在设计期间改变PMOS和NMOS晶体管的尺寸以满足功率需求。根据功率要求，可以使用多个PMOS和NMOS晶体管。 PMOS和NMOS晶体管的组合允许使用有限的制造工艺，其中可以限制晶体管宽度。

28. 发明授权

US07091766B2 Retention register for system-transparent state retention 有权
标题翻译：保留注册表，用于系统透明状态保留
公开(公告)号：US07091766B2
公开(公告)日：2006-08-15
申请号：US10616207
申请日：2003-07-03
申请人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh Mair
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh Mair
IPC分类号： H03K3/12 , H03K3/37 , H03K3/286 , H03K3/356
CPC分类号： H03K3/356008
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的节点（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作，用于实现状态保留功能。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

29. 发明授权

US06956398B1 Leakage current reduction method 有权
标题翻译：泄漏电流还原法
公开(公告)号：US06956398B1
公开(公告)日：2005-10-18
申请号：US10806624
申请日：2004-03-23
申请人： Hugh Mair , Luan A. Dang , Xiaowei Deng , George B. Jamison , Tam M. Tran , Shyh-Horng Yang , David B. Scott
发明人： Hugh Mair , Luan A. Dang , Xiaowei Deng , George B. Jamison , Tam M. Tran , Shyh-Horng Yang , David B. Scott
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003
CPC分类号： H03K19/00361 , H03K19/0016
摘要： The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.
摘要翻译：用于为数据保持模式断电的方法包括：将电源电压节点从有功功率电压电平改变为无功功率电平; 将P沟道器件的源极耦合到电源电压节点; 向P通道装置的后门提供保持电源电压电平; 将P沟道器件的漏极电压改变到参考电压电平，其中所述参考电压电平不同于所述保持电源电压电平; 并将P沟道器件的栅极电压改变到参考电压电平。

30. 发明授权

US5544599A Program controlled quilter and panel cutter system with automatic shrinkage compensation 失效
标题翻译：自动收缩补偿程序控制绗缝机和面板切割机系统
公开(公告)号：US5544599A
公开(公告)日：1996-08-13
申请号：US271420
申请日：1994-07-06
申请人： James T. Frazer , David B. Scott , James F. Bondanza
发明人： James T. Frazer , David B. Scott , James F. Bondanza
IPC分类号： B65H35/00 , D05B11/00 , D06H7/02
CPC分类号： D05B11/00 , B65H35/006 , D06H7/02 , B65H2511/512 , D05D2305/12 , D05D2305/32
摘要： A quilting machine includes a multiple needle quilter with a panel cutter located in-line therewith and downstream thereof and having an accumulator therebetween. A programmable controller operates the quilter to stitch a programmed series of one or more patterns on a web. A feed roller angular encoder measures the quilted web length fed under tension to the accumulator. A detector signals when the accumulator is full, whereupon the controller causes web to be fed from the accumulator to the panel cutter, where it passes without tension thereon toward a photo sensor. The photo sensor signals the controller which activates the cutter to sever a predetermined panel length from the web. The controller then reads information from the encoder and the accumulator detector to determine the amount of stressed quilt required to replenish the cutoff panel length. The ratio of measurements is then processed to determine the elongation change or "shrinkage", which information is used to control the relative feed at the quilter, cutter and fabric supply and to track the quilted patterns and splices in the fabric of the web through the machine.
摘要翻译：一种绗缝机包括一个多针绗缝机，一个面板切割机与其一起位于其下游，并具有一个储液器。可编程控制器操作绗缝机，将一系列一个或多个图案缝合在网上。进料辊角度编码器测量在张力下进给蓄能器的绗缝卷材长度。当蓄能器充满时，检测器发出信号，于是控制器使纤维网从蓄能器进给到面板切割器，其中它通过而不向其照射传感器。光传感器用信号通知控制器，该控制器激活切割器以从纸幅切断预定的面板长度。然后，控制器从编码器和累加器检测器读取信息，以确定补充截止面板长度所需的受力被子的量。然后处理测量的比率以确定伸长率变化或“收缩”，该信息用于控制在绗缝机，切割机和织物供应处的相对进料，并且跟踪幅材织物中的绗缝图案和接头通过机。

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