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21. 发明申请

US20070254435A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A FIN AN STRUCTURE THEREOF 有权
标题翻译：用于形成具有其结构的半导体器件的方法
公开(公告)号：US20070254435A1
公开(公告)日：2007-11-01
申请号：US11380530
申请日：2006-04-27
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： A method for forming a semiconductor device includes providing a semiconductor layer, forming a passivation layer over the semiconductor layer, wherein the passivation layer has an opening having sidewalls, forming a fin over the semiconductor layer, wherein after forming the passivation layer the fin is within the opening, and forming a portion of a gate within the opening. In one embodiment, a dummy gate is used. In one embodiment, spacers are formed within the opening of the passivation layer. The structure is also discussed.
摘要翻译：一种用于形成半导体器件的方法包括提供半导体层，在该半导体层上形成钝化层，其中该钝化层具有一个具有侧壁的开口，在该半导体层上形成鳍状物，其中在形成钝化层之后，鳍片在其内开口，并且在开口内形成门的一部分。在一个实施例中，使用虚拟门。在一个实施例中，在钝化层的开口内形成间隔物。还讨论了结构。

22. 发明授权

US07279433B2 Deposition and patterning of boron nitride nanotube ILD 有权
标题翻译：氮化硼纳米管的沉积和图案ILD
公开(公告)号：US07279433B2
公开(公告)日：2007-10-09
申请号：US10945319
申请日：2004-09-20
申请人： Peter L. G. Ventzek , Kurt Junker , Marius Orlowski
发明人： Peter L. G. Ventzek , Kurt Junker , Marius Orlowski
IPC分类号： H01L21/31
CPC分类号： H01L21/02112 , B82Y10/00 , H01L21/02282 , H01L21/318 , H01L21/76801 , H01L21/76813 , H01L21/76819 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a dielectric layer is disclosed herein. In accordance with the method, a first material is provided (303) which comprises a suspension of nanoparticles in a liquid medium. A dielectric layer is then formed (305) on the substrate from the suspension through an evaporative process.
摘要翻译：本文公开了形成电介质层的方法。根据该方法，提供第一材料（303），其包括纳米颗粒在液体介质中的悬浮液。然后通过蒸发过程从悬浮液在基底上形成介电层（305）。

23. 发明申请

US20070231946A1 Laterally grown nanotubes and method of formation 有权
标题翻译：侧生长的纳米管和形成方法
公开(公告)号：US20070231946A1
公开(公告)日：2007-10-04
申请号：US11240241
申请日：2005-09-30
申请人： Marius Orlowski , Shahid Rauf , Peter Ventzek
发明人： Marius Orlowski , Shahid Rauf , Peter Ventzek
IPC分类号： H01L51/40 , H01L51/00 , H01L35/24 , H01L29/08
CPC分类号： H01L21/76838 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/89 , Y10S977/891 , Y10S977/932 , Y10S977/939 , H01L2924/00
摘要： A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts.
摘要翻译：半导体器件具有由碳纳米管形成的横向导体或迹线。覆盖衬底上形成牺牲层。覆盖在牺牲层上的电介质层。通过去除位于两列金属催化剂之间的介电层和牺牲层的一部分来形成侧向开口。横向开口包括颈部和空腔部分，其用作用于生长纳米管的约束空间。使用等离子体来施加形成控制纳米管形成方向的电场的电荷。来自每列金属催化剂的纳米管横向生长并邻接或合并成一个纳米管。与纳米管的接触可以由金属催化剂的颈部或者柱子制成。

24. 发明申请

US20070173024A1 Method for producing two gates controlling the same channel 有权
公开(公告)号：US20070173024A1
公开(公告)日：2007-07-26
申请号：US11339101
申请日：2006-01-25
申请人： Sinan Goktepeli , Alexander Hoefler , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Hoefler , Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , H01L21/823437 , H01L21/823468 , H01L27/0705 , H01L29/66484 , H01L29/7831
摘要： A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate channel (71) subsequently defined in the substrate (11) by source/drain regions (82, 102, 84, 104) that are implanted around the etched gate structures (72, 74). Depending on how the first spacer structure (42) is positioned and configured, the channel (71) may be controlled to provide either a logical AND gate (100) or logical OR gate (200) functionality.

25. 发明申请

US20070026593A1 Diffusion barrier for nickel silicides in a semiconductor fabrication process 有权
标题翻译：半导体制造工艺中硅化镍的扩散阻挡层
公开(公告)号：US20070026593A1
公开(公告)日：2007-02-01
申请号：US11192968
申请日：2005-07-29
申请人： Dharmesh Jawarani , Chun-Li Liu , Marius Orlowski
发明人： Dharmesh Jawarani , Chun-Li Liu , Marius Orlowski
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/665 , H01L29/1083 , H01L29/4925 , H01L29/66636 , H01L29/7834
摘要： A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier “curtains” on sidewalls of the source/drain recesses. A metal layer is deposited wherein the metal layer contacts a semiconductor within the recess. The wafer is annealed to form a silicide selectively. The diffusivity of the metal with respect to the barrier structure material is an order of magnitude less than the diffusivity of the metal with respect to the semiconductor material. The etched recesses may include re-entrant sidewalls. The metal layer may be a nickel layer and the barrier layer may be a titanium nitride layer. Silicon or silicon germanium epitaxial structures may be formed in the recesses overlying the semiconductor substrate.
摘要翻译：半导体制造方法包括形成覆盖在基板上的栅极模块。使用栅极模块作为掩模在衬底中蚀刻凹陷。阻挡层沉积在晶片上并进行各向异性蚀刻以在源极/漏极凹槽的侧壁上形成屏障“窗帘”。沉积金属层，其中金属层与凹槽内的半导体接触。将晶片退火以选择性地形成硅化物。金属相对于阻挡结构材料的扩散率比金属相对于半导体材料的扩散率小一个数量级。蚀刻的凹槽可以包括再入口侧壁。金属层可以是镍层，阻挡层可以是氮化钛层。可以在覆盖半导体衬底的凹部中形成硅或硅锗外延结构。

26. 发明申请

US20060094169A1 Semiconductor device structure and method therefor 有权
标题翻译：半导体器件结构及其方法
公开(公告)号：US20060094169A1
公开(公告)日：2006-05-04
申请号：US10977423
申请日：2004-10-29
申请人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
发明人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

27. 发明申请

US20060043498A1 Method and apparatus for performance enhancement in an asymmetrical semiconductor device 有权
标题翻译：用于不对称半导体器件中的性能增强的方法和装置
公开(公告)号：US20060043498A1
公开(公告)日：2006-03-02
申请号：US10924650
申请日：2004-08-24
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
摘要翻译：提出了一种在半导体器件中提供性能增强的方法和装置。在一个实施例中，第一电流区域（64,76,23），沟道区域和第二电流区域（75,33,66）彼此相邻。第二电流区域（75,33,66）具有比第一电流区域（64,76,23）中的第一元件的含量大的合金的第一元素的含量，其中第二电流区域（75，所述第一元件的含量大于所述沟道区域中的所述第一元素的含量，所述合金还包括第二元素，所述第一元素具有第一价数，并且所述第二元素具有第二价数。此外，第一价数和第二价数之和为八。

28. 发明申请

US20050070056A1 SOI template layer 有权
标题翻译： SOI模板层
公开(公告)号：US20050070056A1
公开(公告)日：2005-03-31
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
发明人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

29. 发明申请

US20050064669A1 Method for forming a semiconductor device having isolation regions 有权
公开(公告)号：US20050064669A1
公开(公告)日：2005-03-24
申请号：US10668714
申请日：2003-09-23
申请人： Marius Orlowski , Alexander Barr
发明人： Marius Orlowski , Alexander Barr
IPC分类号： H01L21/336 , H01L21/762 , H01L29/78 , H01L21/76
CPC分类号： H01L29/66628 , H01L21/76235 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device having isolation structures decreases leakage current. A channel isolation structure decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures are formed under current electrode regions to prevent leakage between the current electrodes.

30. 发明授权

US06433382B1 Split-gate vertically oriented EEPROM device and process 失效
标题翻译：分离式垂直方向的EEPROM器件和工艺
公开(公告)号：US06433382B1
公开(公告)日：2002-08-13
申请号：US08417537
申请日：1995-04-06
申请人： Marius Orlowski , Kuo-Tung Chang , Keith E. Witek , Jon Fitch
发明人： Marius Orlowski , Kuo-Tung Chang , Keith E. Witek , Jon Fitch
IPC分类号： H01L29788
CPC分类号： H01L29/7885 , G11C16/0433 , H01L29/42324
摘要： A split-gate EEPROM transistor includes a channel region (22) formed in a vertically disposed semiconductor body (58) and residing intermediate to a drain region (26) and a source region (24). A select gate electrode (28) is horizontally disposed on a semiconductor substrate (20). A floating gate electrode (30) resides adjacent to the channel region (22) and overlies the select gate electrode (28). A control gate electrode (32) resides adjacent to the control gate electrode (30) and also overlies the select gate electrode (28). In operation, the select gate electrode (28) regulates the flow of electrical charge from the source region (24) into the channel region (22), and provides a field plate electrical isolation for adjacent memory cells in an EEPROM array.
摘要翻译：分闸门EEPROM晶体管包括形成在垂直布置的半导体本体（58）中并且位于中间到漏极区（26）和源极区（24）的沟道区（22）。选择栅电极（28）水平地设置在半导体衬底（20）上。浮栅电极（30）位于与沟道区（22）相邻并且覆盖选择栅电极（28）。控制栅电极（32）位于与控制栅电极（30）相邻并且也覆盖选择栅电极（28）。在操作中，选择栅极（28）调节从源极区域（24）到沟道区域（22）的电荷流动，并为EEPROM阵列中的相邻存储器单元提供场板电隔离。

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