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21. 发明授权

US06869888B1 E-beam flood exposure of spin-on material to eliminate voids in vias 失效
标题翻译：旋转材料的电子束暴露以消除通孔中的空隙
公开(公告)号：US06869888B1
公开(公告)日：2005-03-22
申请号：US09901704
申请日：2001-07-11
申请人： Marina V. Plat , Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh
发明人： Marina V. Plat , Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh
IPC分类号： H01L21/027 , H01L21/3105 , H01L21/312 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02134 , H01L21/0276 , H01L21/31058 , H01L21/312 , H01L21/76825
摘要： A method for forming a semiconductor device is described. The method comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. The BARC layer is exposed to an electron beam (e-beam) so that the BARC layer reaches a flow temperature in the at least one hole. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the BARC layer in the at least one hole acts as an etch resistant layer during the etch.
摘要翻译：对半导体装置的形成方法进行说明。该方法包括在半导体衬底上形成第一层。通过第一层形成至少一个孔。在至少一个孔中形成底部抗反射涂层（BARC）层。 BARC层暴露于电子束（电子束），使得BARC层在至少一个孔中达到流动温度。执行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的BARC层在蚀刻期间用作耐蚀刻层。

22. 发明授权

US06326231B1 Use of silicon oxynitride ARC for metal layers 有权
标题翻译：氧氮化硅ARC用于金属层
公开(公告)号：US06326231B1
公开(公告)日：2001-12-04
申请号：US09207562
申请日：1998-12-08
申请人： Ramkumar Subramanian , Bhanwar Singh , Sanjay K. Yedur , Marina V. Plat , Christopher F. Lyons , Bharath Rangarajan , Michael K. Templeton
发明人： Ramkumar Subramanian , Bhanwar Singh , Sanjay K. Yedur , Marina V. Plat , Christopher F. Lyons , Bharath Rangarajan , Michael K. Templeton
IPC分类号： H01L2100
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/3143 , H01L21/3145
摘要： In one embodiment, the present invention relates to a method of forming a silicon oxynitride antireflection coating over a metal layer, involving the steps of providing a semiconductor substrate comprising the metal layer over at least part of the semiconductor substrate; depositing a silicon oxynitride layer over the metal layer having a thickness from about 100 Å to about 150 Å; and forming an oxide layer having a thickness from about 5 Å to about 50 Å over the silicon oxynitride layer to provide the silicon oxynitride antireflection coating. In another embodiment, the present invention relates to a method of reducing an apparent reflectivity of a metal layer having a first reflectivity in a semiconductor structure, involing forming a silicon oxynitride antireflection coating over the metal layer; wherein the silicon oxynitride antireflection coating formed over the metal layer has a second reflectivity and is formed by depositing silicon oxynitride on the metal layer by chemical vapor deposition and forming an oxide layer over the oxynitride, and the difference between the first reflectivity and the second reflectivity is at least about 60%.
摘要翻译：在一个实施方案中，本发明涉及在金属层上形成氮氧化硅抗反射涂层的方法，包括以下步骤：在半导体衬底的至少一部分上提供包括金属层的半导体衬底; 在所述金属层上沉积厚度为约至约的氧氮化硅层; 并在氮氧化硅层上形成厚度约为5-20埃的氧化物层，以提供氮氧化硅抗反射涂层。在另一个实施方案中，本发明涉及一种在半导体结构中减少具有第一反射率的金属层的表观反射率的方法，包括在金属层上形成氮氧化硅抗反射涂层; 其中形成在所述金属层上的所述氧氮化硅抗反射涂层具有第二反射率，并且通过化学气相沉积在所述金属层上沉积氧氮化硅并在所述氧氮化物上形成氧化物层，并且所述第一反射率和所述第二反射率之间的差异至少约60％。

23. 发明授权

US06900124B1 Patterning for elliptical Vss contact on flash memory 有权
标题翻译：闪存上的椭圆形Vss接触图案化
公开(公告)号：US06900124B1
公开(公告)日：2005-05-31
申请号：US10654739
申请日：2003-09-03
申请人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译：公开了一种在闪速存储器件中形成触点的方法。该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。导电层沉积在接触孔中，去除过量的导电材料。

24. 发明授权

US06558965B1 Measuring BARC thickness using scatterometry 失效
标题翻译：使用散点测量BARC厚度
公开(公告)号：US06558965B1
公开(公告)日：2003-05-06
申请号：US09901702
申请日：2001-07-11
申请人： Bhanwar Singh , Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat
发明人： Bhanwar Singh , Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat
IPC分类号： H01L2166
CPC分类号： G03F7/091 , G01B11/0616 , H01L21/0276
摘要： A method of forming a semiconductor device is described. A bottom anti-reflective coating (BARC) is formed in a plurality of holes and on a first surface of a layer of a semiconductor device. A scatterometry measurement on at least a portion of the BARC is performed to produce measurement diffraction data. A thickness of the BARC in the plurality of holes is predicted by comparing the first diffraction data to a model of diffraction data to provide a predicted thickness, tp, and it is determined if the predicted thickness, tp, is within a target thickness range, &Dgr;td. The forming of the BARC is controlled in response to the prediction of the BARC thickness. A corresponding thickness control device for controlling the BARC thickness is also disclosed.
摘要翻译：描述形成半导体器件的方法。底部抗反射涂层（BARC）形成在多个孔中以及在半导体器件的层的第一表面上。执行至少一部分BARC的散射测量以产生测量衍射数据。通过将第一衍射数据与衍射数据的模型进行比较以提供预测厚度tp来预测多个孔中的BARC的厚度，并且确定预测厚度tp是否在目标厚度范围内， DELTAtd。响应于BARC厚度的预测，控制BARC的形成。还公开了用于控制BARC厚度的相应的厚度控制装置。

25. 发明授权

US07122455B1 Patterning with rigid organic under-layer 有权
标题翻译：图案与刚性有机底层
公开(公告)号：US07122455B1
公开(公告)日：2006-10-17
申请号：US10790567
申请日：2004-03-01
申请人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
发明人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28035 , H01L21/28123 , Y10S438/942 , Y10S438/947
摘要： For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.
摘要翻译：为了图案化IC（集成电路）材料，在IC材料之上形成刚性有机底层，并且将刚性有机底层图案化以形成刚性有机掩模结构。此外，修剪刚性有机掩模结构以降低刚性有机掩模结构的临界尺寸超出传统BARC掩模结构的限制。不会在刚性有机掩模结构下面的IC材料的任何部分被蚀刻掉以形成IC结构。

26. 发明授权

US07268066B2 Method for semiconductor gate line dimension reduction 有权
标题翻译：半导体栅极线尺寸减小的方法
公开(公告)号：US07268066B2
公开(公告)日：2007-09-11
申请号：US10922093
申请日：2004-08-19
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
IPC分类号： H01L21/4763
CPC分类号： H01L29/66477 , H01L21/28123 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
摘要翻译：为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。所形成的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。

27. 发明授权

US06864556B1 CVD organic polymer film for advanced gate patterning 失效
标题翻译：用于先进栅极图案化的CVD有机聚合物膜
公开(公告)号：US06864556B1
公开(公告)日：2005-03-08
申请号：US10335445
申请日：2002-12-31
申请人： Lu You , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Richard J. Huang , Christopher F. Lyons , Mark S. Chang , Marilyn I. Wright
发明人： Lu You , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Richard J. Huang , Christopher F. Lyons , Mark S. Chang , Marilyn I. Wright
IPC分类号： G03F7/09 , H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/47 , H01L31/0232
CPC分类号： H01L21/32139 , G03F7/091 , H01L21/0332 , H01L21/28123 , H01L29/785
摘要： A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.
摘要翻译：采用底层抗反射涂层，其包含基本上不含氮的有机聚合物层和相对于多晶硅层的低压缩应力作为双层抗反射涂层/硬掩模结构的下层，以减少图案的变形形成在可图案层中。有机聚合物层对可见辐射基本上是透明的，能够在半导体器件制造过程中更好地检测对准标记并提高覆盖精度。有机聚合物层提供优异的台阶覆盖，并且可以有利地用于制造诸如FinFET的结构。

28. 发明授权

US06764949B2 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication 有权
公开(公告)号：US06764949B2
公开(公告)日：2004-07-20
申请号：US10334392
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2144
CPC分类号： H01L21/32139 , H01L21/0332
摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

29. 发明授权

US06849530B2 Method for semiconductor gate line dimension reduction 失效
公开(公告)号：US06849530B2
公开(公告)日：2005-02-01
申请号：US10334337
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
IPC分类号： H01L21/28 , H01L21/4763
CPC分类号： H01L21/28123
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

30. 发明授权

US06773998B1 Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning 有权
标题翻译：改进的薄膜堆叠和图案化策略，用于应力补偿和防止无定形碳栅图案中的图案变形
公开(公告)号：US06773998B1
公开(公告)日：2004-08-10
申请号：US10445129
申请日：2003-05-20
申请人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
发明人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21336
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/3146 , H01L21/32137 , H01L21/32139
摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.
摘要翻译：集成电路的方法包括使用无定形碳ARC掩模。一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

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