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1. 发明授权

US07018922B1 Patterning for elongated VSS contact flash memory 有权
标题翻译：扩展VSS接触闪存的图案化
公开(公告)号：US07018922B1
公开(公告)日：2006-03-28
申请号：US10968713
申请日：2004-10-19
申请人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译：公开了一种在闪速存储器件中形成触点的方法。该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。导电层沉积在接触孔中，去除过量的导电材料。

2. 发明授权

US06900124B1 Patterning for elliptical Vss contact on flash memory 有权
标题翻译：闪存上的椭圆形Vss接触图案化
公开(公告)号：US06900124B1
公开(公告)日：2005-05-31
申请号：US10654739
申请日：2003-09-03
申请人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译：公开了一种在闪速存储器件中形成触点的方法。该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。导电层沉积在接触孔中，去除过量的导电材料。

3. 发明授权

US07368225B1 Two mask photoresist exposure pattern for dense and isolated regions 有权
标题翻译：两个掩模光刻胶曝光图案，用于密集和隔离的区域
公开(公告)号：US07368225B1
公开(公告)日：2008-05-06
申请号：US10925123
申请日：2004-08-24
申请人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eil Kim
发明人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eil Kim
IPC分类号： G03F7/00
CPC分类号： G03F1/00 , H01L21/76816
摘要： There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.
摘要翻译：提供了在第一层中制作多个特征的方法。在第一层上形成光致抗蚀剂层。光致抗蚀剂层中的密集区域在第一组照射条件下通过第一掩模曝光。在与第一组照明条件不同的第二组照明条件下，光致抗蚀剂层中的隔离区域通过不同于第一掩模的第二掩模曝光。曝光的光致抗蚀剂层被图案化，然后使用图案化的光致抗蚀剂层作为掩模来对第一层进行图案化。

4. 发明授权

US06689541B1 Process for forming a photoresist mask 有权
标题翻译：光刻胶掩模形成工艺
公开(公告)号：US06689541B1
公开(公告)日：2004-02-10
申请号：US09884182
申请日：2001-06-19
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： G03C500
CPC分类号： G03F7/38 , G03F7/265 , G03F7/40
摘要： In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.
摘要翻译：在形成光致抗蚀剂掩模的工艺中，将光致抗蚀剂层施加到基底上。在光致抗蚀剂层中形成硅化层。硅酸盐化区域的特征对应于要形成的光致抗蚀剂掩模的特征。然后蚀刻光致抗蚀剂层以在硅化区域下方形成光致抗蚀剂基底。蚀刻光致抗蚀剂基底以从其侧面去除材料，使得它比斯里芬特区域变窄。然后除去硅酸盐化区域，在基材上留下光刻胶掩模。

5. 发明授权

US06605546B1 Dual bake for BARC fill without voids 失效
标题翻译：双烘烤BARC填充无空隙
公开(公告)号：US06605546B1
公开(公告)日：2003-08-12
申请号：US09901699
申请日：2001-07-11
申请人： Ramkumar Subramanian , Wolfram Grundke , Bhanwar Singh , Christopher F. Lyons , Marina V. Plat
发明人： Ramkumar Subramanian , Wolfram Grundke , Bhanwar Singh , Christopher F. Lyons , Marina V. Plat
IPC分类号： H01L21302
CPC分类号： H01L21/76808
摘要： A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.
摘要翻译：一种用于形成半导体器件的方法包括在半导体衬底上形成第一层。通过第一层形成至少一个孔。在至少一个孔中形成底部抗反射涂层（BARC）层。执行第一次加热以将BARC层加热至流动温度。执行第二次加热以将BARC层加热至硬化温度，使得BARC层硬化，其中硬化温度大于流动温度。进行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的硬化的BARC层在蚀刻期间用作耐蚀刻层。作为第二加热步骤的替代方案，BARC可以简单地硬化。第一和第二加热可以在加热室内进行，而不去除半导体衬底。

6. 发明授权

US06563221B1 Connection structures for integrated circuits and processes for their formation 失效
标题翻译：集成电路的连接结构及其形成过程
公开(公告)号：US06563221B1
公开(公告)日：2003-05-13
申请号：US10081982
申请日：2002-02-21
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L2348
CPC分类号： H01L21/76885 , H01L21/76831 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In a method for forming a connection structure in an integrated circuit, a first conducting material is deposited over a substrate and patterned to form a conducting stud in electrical contact with a conducting element of the substrate. A dielectric is formed over the substrate and the conducting stud. A trench is formed in the dielectric to expose a top portion of the conducting stud, and a second conducting material is inlaid in the trench to form wiring in electrical contact with the conducting stud. The electrically conducting element of the substrate may be an element of a semiconductor device or a wiring, contact or via. The first conducting material may be aluminum, and the second conducting material may be copper. The dielectric may be formed as a single layer and may be an organic low-k dielectric. Related connection structures are also disclosed.
摘要翻译：在用于在集成电路中形成连接结构的方法中，第一导电材料沉积在衬底上并被图案化以形成与衬底的导电元件电接触的导电柱。电介质形成在衬底和导电柱上。在电介质中形成沟槽以暴露导电柱的顶部，并且第二导电材料镶嵌在沟槽中以形成与导电柱电接触的布线。衬底的导电元件可以是半导体器件或布线，接触或通孔的元件。第一导电材料可以是铝，第二导电材料可以是铜。电介质可以形成为单层，并且可以是有机低k电介质。还公开了相关的连接结构。

7. 发明授权

US06534418B1 Use of silicon containing imaging layer to define sub-resolution gate structures 有权
标题翻译：使用含硅成像层来定义次分辨率门结构
公开(公告)号：US06534418B1
公开(公告)日：2003-03-18
申请号：US09845656
申请日：2001-04-30
申请人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
发明人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L21302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/28123 , H01L29/6659 , H01L29/7833
摘要： An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
摘要翻译：使用含硅成像层来限定次分辨率门结构的示例性方法可以包括在多晶硅层上沉积抗反射涂层，在抗反射涂层上沉积成像层，选择性地蚀刻抗反射涂层以形成使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用修剪蚀刻技术，而不会有抗蚀剂侵蚀或高宽比图案崩溃的风险。这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

8. 发明授权

US06458691B1 Dual inlaid process using an imaging layer to protect via from poisoning 有权
标题翻译：双镶嵌工艺使用成像层保护通孔免受中毒
公开(公告)号：US06458691B1
公开(公告)日：2002-10-01
申请号：US09824662
申请日：2001-04-04
申请人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
发明人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/76807
摘要： There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming an inorganic base radiation sensitive layer in the first opening. The radiation sensitive layer may be a polysilane imaging layer. The inorganic base radiation sensitive layer is selectively exposed to radiation and then patterned. A second opening, such a trench, is formed in communication with the first opening using the patterned inorganic base radiation sensitive layer as a mask. A conductive layer may be formed in the dual inlaid via to complete a dual damascene process.
摘要翻译：提供了在第一层中制作双重嵌入通孔的方法。第一层可以是半导体器件的聚合物金属间电介质，例如HSQ。该方法包括在第一层中形成诸如通孔的第一开口，并在第一开口中形成无机碱辐射敏感层。辐射敏感层可以是聚硅烷成像层。无机碱辐射敏感层选择性地暴露于辐射，然后图案化。使用图案化的无机基底辐射敏感层作为掩模，形成与第一开口连通的第二开口，这样的沟槽。可以在双镶嵌通孔中形成导电层以完成双镶嵌工艺。

9. 发明授权

US06358856B1 Bright field image reversal for contact hole patterning 有权
标题翻译：接触孔图案的亮场图像反转
公开(公告)号：US06358856B1
公开(公告)日：2002-03-19
申请号：US09716215
申请日：2000-11-21
申请人： Christopher F. Lyons , Ramkumar Subramanian , Marina V. Plat , Todd P. Lukanc
发明人： Christopher F. Lyons , Ramkumar Subramanian , Marina V. Plat , Todd P. Lukanc
IPC分类号： H01L21311
CPC分类号： H01L21/31144
摘要： A method of forming a small contact hole uses a bright field mask to form a small cylinder in a positive resist layer. A negative resist layer is formed around the small cylinder, and then etched or polished back to leave a top portion of the small cylinder exposed above the negative resist layer. The negative resist layer and the small cylinder (positive resist) are flood exposed to light, and then subject to a developer. What remains is a small contact hole located where the small cylinder was previously located.
摘要翻译：形成小接触孔的方法使用亮场掩模在正抗蚀剂层中形成小圆筒。在小圆筒周围形成负的抗蚀剂层，然后被蚀刻或抛光回去，使得暴露在负性抗蚀剂层上方的小圆筒的顶部部分留下。负抗蚀剂层和小圆筒（正性抗蚀剂）暴露于光下，然后经受显影剂。剩下的是一个位于小圆柱之前所在的小接触孔。

10. 发明授权

US06753266B1 Method of enhancing gate patterning properties with reflective hard mask 有权
标题翻译：用反射硬掩模增强栅极图案化性能的方法
公开(公告)号：US06753266B1
公开(公告)日：2004-06-22
申请号：US09845654
申请日：2001-04-30
申请人： Todd P. Lukanc , Scott A. Bell , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Todd P. Lukanc , Scott A. Bell , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21309
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/823828
摘要： An exemplary method of fabricating an integrated circuit can include depositing a reflective metal material layer over a layer of polysilicon, depositing an anti-reflective coating over the reflective metal material layer, trim etching the anti-reflective coating to form a pattern, etching the reflective metal material layer according to the pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating.
摘要翻译：制造集成电路的示例性方法可以包括在多晶硅层上沉积反射金属材料层，在反射金属材料层上沉积抗反射涂层，修整蚀刻抗反射涂层以形成图案，蚀刻反射金属材料层，并且使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。

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