专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20050139525A1 Chip sorting apparatus and method for fabricating the same 审中-公开
标题翻译：芯片分选装置及其制造方法
公开(公告)号：US20050139525A1
公开(公告)日：2005-06-30
申请号：US10722507
申请日：2003-11-28
申请人： Tung-Hung Tsai , Shyang-Li Wang , Chia-Wei Wu , Jhih-Jhong Huang
发明人： Tung-Hung Tsai , Shyang-Li Wang , Chia-Wei Wu , Jhih-Jhong Huang
IPC分类号： B07C5/344 , B07C5/00
CPC分类号： B07C5/344
摘要： A chip sorting apparatus and a method for fabricating the same are applicable to the chip pick-up sorting process after chip formation. By using the chip sorting apparatus and the method for fabricating the same in the chip pick-up process, it can directly inspect the chip without multiple chip movements for implementing the chip inspection. The chip sorting apparatus and the method for fabricating the same use a positioning axis to directly process inspection on the chip before picking up the chip. This, therefore, can avoid the complicated process causing from multiple chip pick-up positions. Further, it can enhance the chip pick-up efficiency.
摘要翻译：芯片分选装置及其制造方法适用于芯片形成后的芯片拾取分拣处理。通过在芯片拾取过程中使用芯片分选装置及其制造方法，可以直接检查芯片而不需要多个芯片移动来实现芯片检查。芯片分选装置及其制造方法使用定位轴来直接处理在拾取芯片之前的芯片上的检查。因此，可以避免由多个芯片拾取位置引起的复杂过程。此外，它可以提高芯片拾取效率。

22. 发明授权

US08466508B2 Non-volatile memory structure including stress material between stacked patterns 有权
标题翻译：非易失性存储器结构，包括层叠图案之间的应力材料
公开(公告)号：US08466508B2
公开(公告)日：2013-06-18
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/792 , H01L29/788 , H01L21/762
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

23. 发明授权

US07588443B2 Board-to-board electrical connector assembly 有权
标题翻译：板对板电连接器组件
公开(公告)号：US07588443B2
公开(公告)日：2009-09-15
申请号：US11890869
申请日：2007-08-08
申请人： Chun-Kwan Wu , Tien-Chieh Su , Chia-Wei Wu , Ming-Tsung Chiang
发明人： Chun-Kwan Wu , Tien-Chieh Su , Chia-Wei Wu , Ming-Tsung Chiang
IPC分类号： H01R12/00
CPC分类号： H01R12/52
摘要： A board-to-board connector assembly includes a first connector (100) having a first housing (10) defining two opposite first longitudinal peripheral walls (11a) and two opposite first transverse peripheral walls (11b) connecting the first longitudinal walls. A rib (114) and a locking portion (116) are respectively defined in corresponding inner wall of the first longitudinal and transverse peripheral walls. A second connector (200) comprises a second housing (30), a plurality of terminals (40) received in the second housing and a pair of metal ears (50) engaged with two opposite second peripheral walls. The terminal and the metal ear respectively define a protrusion (431) and a projection (54) extending outward thereof and snugly fit against the corresponding rib and the locking portion when the first and second connectors engage with each other.
摘要翻译：板对板连接器组件包括具有限定两个相对的第一纵向周壁（11a）的第一壳体（10）和连接第一纵向壁的两个相对的第一横向周壁（11b）的第一连接器（100）。肋（114）和锁定部分（116）分别限定在第一纵向和横向周壁的对应的内壁中。第二连接器（200）包括第二壳体（30），容纳在第二壳体中的多个端子（40）和与两个相对的第二周壁接合的一对金属耳（50）。端子和金属耳分别限定突起（431）和向外延伸的突出部（54），并且当第一和第二连接器彼此接合时，紧密地配合抵靠相应的肋和锁定部。

24. 发明申请

US20090011574A1 Method for surface modification of semiconductor layer and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体层的表面改性方法及半导体装置的制造方法
公开(公告)号：US20090011574A1
公开(公告)日：2009-01-08
申请号：US11822076
申请日：2007-07-02
申请人： Wei-Yao Tang , Chia-Wei Wu
发明人： Wei-Yao Tang , Chia-Wei Wu
IPC分类号： H01L21/20 , C23G1/02
CPC分类号： H01L21/02068 , H01L21/2652 , H01L21/28035 , H01L21/28105 , H01L29/66575
摘要： A method for surface modification of a semiconductor layer and a method of manufacturing a semiconductor device are provided. The method for surface modification of the silicon layer includes following steps. First, a semiconductor layer having several particles on its surface is provided. Next, these particles are removed through a clean process. In the clean process, the semiconductor layer is exposed to an organic matter remover, a first peroxide mixture solution and a second peroxide mixture solution sequentially.
摘要翻译：提供了半导体层的表面改性方法以及半导体装置的制造方法。硅层的表面改性方法包括以下步骤。首先，提供在其表面上具有多个颗粒的半导体层。接下来，通过干净的工艺去除这些颗粒。在清洁过程中，依次将半导体层暴露于有机物去除剂，第一过氧化物混合物溶液和第二过氧化物混合物溶液。

25. 发明申请

US20080299741A1 Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation 有权
标题翻译：蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法
公开(公告)号：US20080299741A1
公开(公告)日：2008-12-04
申请号：US11806186
申请日：2007-05-30
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
IPC分类号： H01L21/762 , C09K13/08 , H01L21/31
CPC分类号： H01L21/30604 , C09K13/08 , H01L21/30608 , H01L21/76232
摘要： An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.
摘要翻译：提供蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法。蚀刻溶液用于表面改性半导体衬底。蚀刻溶液包括氧化剂和氧化物去除剂。半导体衬底被氧化剂氧化成半导体氧化物，并且氧化物去除器减去半导体氧化物。

26. 发明申请

US20080238454A1 TESTER AND STRUCTURE OF PROBE THEREOF 有权
标题翻译：探测器及其结构
公开(公告)号：US20080238454A1
公开(公告)日：2008-10-02
申请号：US11745463
申请日：2007-05-08
申请人： Chia-Wei Wu
发明人： Chia-Wei Wu
IPC分类号： G01R1/067 , G01R1/073 , G01R31/26
CPC分类号： G01R1/06772 , G01R1/06727 , G01R1/06733
摘要： A split-type probe is used to contact with an object under test to detect an electrical characteristic thereof. The probe provided by the present invention has a contact head used to contact with the object under test, and a first needle body and a second needle body. The first needle body is connected to the contact head to transmit a testing signal to the object under test for performing detection. In addition, the second needle body is also connected to the contact head to transmit a response signal generated by the object under test due to the testing signal to obtain the electrical characteristic of the object under test.
摘要翻译：分离式探头用于与待测物体接触以检测其电气特性。本发明提供的探针具有用于与待测物体接触的接触头，以及第一针体和第二针体。第一针体连接到接触头，以将测试信号传送到被测物体进行检测。此外，第二针体还连接到接触头，以通过测试信号传输由被测物体产生的响应信号，以获得被测物体的电特性。

27. 发明申请

US20080087946A1 Vertical channel transistor structure and manufacturing method thereof 有权
标题翻译：垂直沟道晶体管结构及其制造方法
公开(公告)号：US20080087946A1
公开(公告)日：2008-04-17
申请号：US11545575
申请日：2006-10-11
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is protruded from the substrate. The cap layer is deposited on the channel. The cap layer and the channel substantially have the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the channel. The gate is deposited on the charge trapping layer and on two vertical surfaces of the channel. The source and the drain are respectively positioned on two sides of the channel and opposing to the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道从基板突出。盖层沉积在通道上。盖层和通道基本上具有相同的宽度。电荷捕获层沉积在封盖层上和通道的两个垂直表面上。栅极沉积在电荷捕获层上和通道的两个垂直表面上。源极和漏极分别位于通道的两侧并与栅极相对。

28. 发明申请

US20080038939A1 Board-to-board electrical connector assembly 有权
标题翻译：板对板电连接器组件
公开(公告)号：US20080038939A1
公开(公告)日：2008-02-14
申请号：US11890869
申请日：2007-08-08
申请人： Chun-Kwan Wu , Tien-Chieh Su , Chia-Wei Wu , Ming-Tsung Chiang , Chia-Shu Tsia
发明人： Chun-Kwan Wu , Tien-Chieh Su , Chia-Wei Wu , Ming-Tsung Chiang , Chia-Shu Tsia
IPC分类号： H01R12/00
CPC分类号： H01R12/52
摘要： A board-to-board connector assembly includes a first connector (100) having a first housing (10) defining two opposite first longitudinal peripheral walls (11a) and two opposite first transverse peripheral walls (11b) connecting the first longitudinal walls. A rib (114) and a locking portion (116) are respectively defined in corresponding inner wall of the first longitudinal and transverse peripheral walls. A second connector (200) comprises a second housing (30), a plurality of terminals (40) received in the second housing and a pair of metal ears (50) engaged with two opposite second peripheral walls. The terminal and the metal ear respectively define a protrusion (431) and a projection (54) extending outward thereof and snugly fit against the corresponding rib and the locking portion when the first and second connectors engage with each other.
摘要翻译：板对板连接器组件包括具有限定两个相对的第一纵向周壁（11a）和连接第一纵向壁的两个相对的第一横向周壁（11b）的第一壳体（10）的第一连接器（100）。肋（114）和锁定部分（116）分别限定在第一纵向和横向周壁的对应的内壁中。第二连接器（200）包括第二壳体（30），容纳在第二壳体中的多个端子（40）和与两个相对的第二周壁接合的一对金属耳（50）。端子和金属耳分别限定突起（431）和向外延伸的突出部（54），并且当第一和第二连接器彼此接合时，紧密地配合抵靠相应的肋和锁定部。

29. 发明申请

US20070134708A1 Diagnostic targets against Johne's disease 审中-公开
标题翻译：诊断针对约翰氏病的目标
公开(公告)号：US20070134708A1
公开(公告)日：2007-06-14
申请号：US11635933
申请日：2006-12-08
申请人： Adel Talaat , Chia-Wei Wu
发明人： Adel Talaat , Chia-Wei Wu
IPC分类号： C12Q1/68 , C07H21/04
CPC分类号： C12Q1/689 , C12Q1/6883
摘要： A composition and method for detecting Mycobacterium infection are disclosed. The gcpE, pstA, kdpC, papA2, impA, umaA1, fabG2132, aceAB, mbtH2, lpqP, map0834c, cspB, lipN, and map 1634 genes of M. paratuberculosis are novel virulence determinants for Johne's disease. Eighteen M. paratuberculosis-specific genomic islands were identified. Twenty-four M. avium-specific genomic islands were identified. Inversion of three large genomic fragments (INV) in M. paratuberculosis was also identified. These genomic identifiers represent novel virulence determinants that can be used as diagnostics targets for mycobacterial infection, and could provide suitable targets for vaccine and drug developments against Johne's disease.
摘要翻译：公开了一种用于检测分枝杆菌感染的组合物和方法。副结核分枝杆菌的gcpE，pstA，kdpC，papA2，impA，umaA1，fabG2 13，aceAB，mbtH2，lpqP，map0834c，cspB，lipN和Map 1634基因是Johne's 疾病。鉴定了十八个副结核分枝杆菌特异性基因组岛。鉴定了二十四只鸟类特异性基因组岛。还鉴定了副结核分枝杆菌中三个大基因组片段（INV）的反转。这些基因组标识符代表可用作分枝杆菌感染诊断目标的新型毒力决定因子，可为针对Johne氏病的疫苗和药物开发提供合适的靶标。

30. 发明申请

US20090276737A1 TOOL FOR CHARGE TRAPPING MEMORY USING SIMULATED PROGRAMMING OPERATIONS 有权
标题翻译：使用模拟编程操作的充电跟踪存储器的工具
公开(公告)号：US20090276737A1
公开(公告)日：2009-11-05
申请号：US12182352
申请日：2008-07-30
申请人： Shaw Hung Ku , Chia-Wei Wu , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Chia-Wei Wu , Ming Shang Chen , Wenpin Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F17/5036 , G06F2217/10 , G06F2217/78
摘要： A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.
摘要翻译：一种用于模拟电荷捕获存储单元的操作的方法，所述电荷捕获存储单元通过确定通过所述隧道层的第一隧道电流来计算所捕获的电荷量，确定从所述电荷俘获层到所述栅极的第二隧穿电流，确定从陷阱中逃逸的第三隧穿电流电荷捕获层并隧穿到栅极，并在一段时间间隔内积分所述隧穿电流。可以对包括电荷捕获结构的晶体管计算阈值电压的变化。参数集可以仅包括物理参数，包括层厚度，带偏移和介电常数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式