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1. 发明授权

US09246015B2 Vertical channel transistor structure and manufacturing method thereof 有权
标题翻译：垂直沟道晶体管结构及其制造方法
公开(公告)号：US09246015B2
公开(公告)日：2016-01-26
申请号：US12892044
申请日：2010-09-28
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/66 , H01L29/792 , H01L27/115 , H01L29/423 , H01L27/12
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道形成为从基板突出的鳍状结构。盖层沉积在鳍状结构上。盖层和鳍状结构具有基本上相同的宽度。电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。源极和漏极分别位于鳍状结构的两侧并与栅极相对。

2. 发明申请

US20080290397A1 MEMORY CELL AND METHOD FOR MANUFACTURING AND OPERATING THE SAME 有权
标题翻译：存储单元及其制造和操作的方法
公开(公告)号：US20080290397A1
公开(公告)日：2008-11-27
申请号：US11753850
申请日：2007-05-25
申请人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection layer and two source/drain regions. The gate is disposed on the substrate,and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The protection layer is disposed between the upper portion of the fin structure and the gate separating the charge trapping structure. The source/drain regions are disposed in the fin structure at both sides of the gate.
摘要翻译：存储单元设置在具有多个隔离结构的衬底上，所述隔离结构在衬底中至少限定翅片结构，其中鳍结构的表面高于隔离结构的表面。存储单元包括栅极，电荷俘获结构，保护层和两个源极/漏极区域。栅极设置在基板上，并跨接在翅片结构上。电荷捕获结构设置在栅极和鳍结构之间。保护层设置在翅片结构的上部和分离电荷捕获结构的栅极之间。源极/漏极区域设置在栅极两侧的鳍结构中。

3. 发明申请

US20110012192A1 Vertical Channel Transistor Structure and Manufacturing Method Thereof 审中-公开
标题翻译：垂直沟道晶体管的结构及制造方法
公开(公告)号：US20110012192A1
公开(公告)日：2011-01-20
申请号：US12892044
申请日：2010-09-28
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道形成为从基板突出的鳍状结构。盖层沉积在鳍状结构上。盖层和鳍状结构具有基本上相同的宽度。电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。源极和漏极分别位于鳍状结构的两侧并与栅极相对。

4. 发明授权

US07811890B2 Vertical channel transistor structure and manufacturing method thereof 有权
标题翻译：垂直沟道晶体管结构及其制造方法
公开(公告)号：US07811890B2
公开(公告)日：2010-10-12
申请号：US11545575
申请日：2006-10-11
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道形成为从基板突出的鳍状结构。盖层沉积在鳍状结构上。盖层和鳍状结构具有基本上相同的宽度。电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。源极和漏极分别位于鳍状结构的两侧并与栅极相对。

5. 发明授权

US07795088B2 Method for manufacturing memory cell 有权
标题翻译：制造存储单元的方法
公开(公告)号：US07795088B2
公开(公告)日：2010-09-14
申请号：US11753850
申请日：2007-05-25
申请人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/28282 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： A method for manufacturing memory cells is provided. First, a substrate is provided, wherein a liner layer and a material layer have already been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the substrate. Then, the patterned mask layer is trimmed. Subsequently, a portion of the material layer, a portion of the liner layer and a portion of the substrate are removed by using the patterned mask layer as a mask to define a plurality of fin-structures in the substrate. Afterward, the patterned mask layer is removed and a plurality of isolation structures among the fin structures is formed. The surface of the isolation structures is lower than that of the fin structures. Following that, charge trapping structures are formed on the substrate, covering the fin structures. Succeeding, a portion of the charge trapping structures is removed to expose the material layer. Then, the treatment process turns the material layer into a protection layer. Subsequently, a gate is formed on the substrate and straddles the protection layer, the charge trapping structures and the fin structure. Afterward, source/drain regions are formed in the fin-structure exposed by both sides of the gate.
摘要翻译：提供一种用于制造存储器单元的方法。首先，提供衬底，其中衬底层和材料层已经顺序形成在衬底上。此后，在衬底上形成图案化掩模层。然后，修整图案化的掩模层。随后，通过使用图案化掩模层作为掩模来去除材料层的一部分，衬垫层的一部分和衬底的一部分，以在衬底中限定多个鳍结构。之后，去除图案化的掩模层，并且形成翅片结构中的多个隔离结构。隔离结构的表面比翅片结构的表面低。之后，在基片上形成电荷俘获结构，覆盖翅片结构。成功地，去除一部分电荷捕获结构以暴露材料层。然后，处理过程将材料层转变成保护层。随后，在基板上形成栅极，跨越保护层，电荷捕获结构和鳍结构。之后，源极/漏极区域形成在由栅极两侧暴露的鳍状结构中。

6. 发明申请

US20080087946A1 Vertical channel transistor structure and manufacturing method thereof 有权
标题翻译：垂直沟道晶体管结构及其制造方法
公开(公告)号：US20080087946A1
公开(公告)日：2008-04-17
申请号：US11545575
申请日：2006-10-11
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is protruded from the substrate. The cap layer is deposited on the channel. The cap layer and the channel substantially have the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the channel. The gate is deposited on the charge trapping layer and on two vertical surfaces of the channel. The source and the drain are respectively positioned on two sides of the channel and opposing to the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道从基板突出。盖层沉积在通道上。盖层和通道基本上具有相同的宽度。电荷捕获层沉积在封盖层上和通道的两个垂直表面上。栅极沉积在电荷捕获层上和通道的两个垂直表面上。源极和漏极分别位于通道的两侧并与栅极相对。

7. 发明申请

US20080128793A1 NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY CELL HAVING ASYMMETRICAL DOPED STRUCTURE 有权
标题翻译：非易失性存储器和非易失性存储单元具有非对称掺杂结构
公开(公告)号：US20080128793A1
公开(公告)日：2008-06-05
申请号：US12017064
申请日：2008-01-21
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792
摘要： A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.
摘要翻译：一种非易失性存储单元，包括衬底，电荷俘获层，控制栅极，源极和漏极的第一导电状态，轻掺杂区域和第二导电状态的袋掺杂区域。电荷捕获层和控制栅极设置在衬底上。电介质层设置在基板，电荷俘获层和控制栅极之间。源极和漏极设置在电荷俘获层的每一侧上的衬底中。轻掺杂区域设置在源极和电荷捕获层之间的衬底表面上。掺杂阱区域设置在漏极和电荷捕获层之间的衬底内。由于存在不对称配置和掺杂导体状态的不同，存储单元的编程速度增加，从而防止了相邻单元的干扰问题，并减少了位线选择晶体管的占用面积。

8. 发明申请

US20080099826A1 Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure, memory arrays including the same and methods of operating the same 有权
标题翻译：具有含多晶硅的多层绝缘结构的非易失性存储单元，包括其的存储器阵列及其操作方法
公开(公告)号：US20080099826A1
公开(公告)日：2008-05-01
申请号：US11588830
申请日：2006-10-27
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/513 , H01L29/66833 , H01L29/792
摘要： Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.
摘要翻译：存储单元包括具有至少两个源极/漏极区域的半导体层，所述源极/漏极区域设置在半导体层的表面下方并被沟道区域分隔开; 设置在通道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 上部绝缘多层结构，其设置在所述电荷存储层上方，其中所述上部绝缘多层结构包括介于第一介电层和第二介电层之间的多晶硅材料层; 并且设置在上绝缘多层结构上方的栅极及其阵列及其操作方法。

9. 发明申请

US20060284243A1 Electrically erasable programmable read only memory (EEPROM) cell and method for making the same 有权
标题翻译：电可擦除可编程只读存储器（EEPROM）单元及其制作方法
公开(公告)号：US20060284243A1
公开(公告)日：2006-12-21
申请号：US11146777
申请日：2005-06-06
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Ming-Hsiu Lee
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Ming-Hsiu Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/7885 , H01L29/7887 , H01L29/7923 , Y10S257/90
摘要： An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction and under the composite charge trapping layer. A P− doped region is positioned adjacent to the second N+ doped junction and under the composite charge trapping layer. The asymmetrically doped memory cell will store charges at the end of the composite charge trapping layer that is above the P− doped region. The asymmetrically doped memory cell can function as an electrically erasable programmable read only memory cell, and is capable of multiple level cell operations. A method for making an asymmetrically doped memory cell is also described.
摘要翻译：不对称掺杂的存储单元在P衬底上具有第一和第二N +掺杂结。复合电荷捕获层设置在P衬底上并且在第一和第二N +掺杂结之间。 N掺杂区域邻近第一N +掺杂结并位于复合电荷俘获层下方。 P-掺杂区域邻近第二N +掺杂结并位于复合电荷俘获层下方。非对称掺杂的存储单元将在复合电荷捕获层的末端在P掺杂区域之上存储电荷。非对称掺杂的存储单元可以用作电可擦除可编程只读存储器单元，并且能够进行多级单元操作。还描述了制造非对称掺杂的存储单元的方法。

10. 发明授权

US08022466B2 Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure, memory arrays including the same and methods of operating the same 有权
标题翻译：具有含多晶硅的多层绝缘结构的非易失性存储单元，包括其的存储器阵列及其操作方法
公开(公告)号：US08022466B2
公开(公告)日：2011-09-20
申请号：US11588830
申请日：2006-10-27
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chih Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/513 , H01L29/66833 , H01L29/792
摘要： Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.
摘要翻译：存储单元包括具有至少两个源极/漏极区域的半导体层，所述源极/漏极区域设置在半导体层的表面下方并被沟道区域分隔开; 设置在通道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 上部绝缘多层结构，其设置在所述电荷存储层上方，其中所述上部绝缘多层结构包括介于第一介电层和第二介电层之间的多晶硅材料层; 并且设置在上绝缘多层结构上方的栅极及其阵列及其操作方法。

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