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21. 发明授权

US07495743B2 Immersion optical lithography system having protective optical coating 失效
标题翻译：具有保护性光学涂层的浸没光学光刻系统
公开(公告)号：US07495743B2
公开(公告)日：2009-02-24
申请号：US11163007
申请日：2005-09-30
申请人： Steven J. Holmes , Toshiharu Furukawa , Charles W. Koburger, III , Naim Moumen
发明人： Steven J. Holmes , Toshiharu Furukawa , Charles W. Koburger, III , Naim Moumen
IPC分类号： G03B27/42 , G03B27/52
CPC分类号： G03F7/2041 , G03F7/11 , G03F7/70341 , G03F7/70958
摘要： An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.
摘要翻译：提供了一种浸没光刻系统，其包括可操作以产生具有标称波长的光和光学成像系统的光源。光学成像系统具有从光源到待图案化的制品的光路中的光学元件。光学元件具有适于接触占据面部和制品之间的空间的液体的面。光学元件包括可被液体降解的材料和覆盖面上的可降解材料以保护面部免受液体的保护涂层，保护涂层对于光是透明的，当暴露于光时稳定，并且当稳定时暴露于液体。

22. 发明授权

US07393779B2 Shrinking contact apertures through LPD oxide 失效
标题翻译：通过LPD氧化物收缩接触孔
公开(公告)号：US07393779B2
公开(公告)日：2008-07-01
申请号：US11163786
申请日：2005-10-31
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.
摘要翻译：通过电介质的亚光刻接触孔形成在电介质，硬掩模和含氧化物种子层的堆叠中。通过种子层的初始孔径通过液相沉积接收氧化物沉积，该相沉积选择性地粘附到种子层中的孔的暴露的垂直壁。通过所添加的材料的厚度减小尺寸的亚光刻孔径在硬掩模中限定了减小的孔径。缩小的硬掩模然后限定通过电介质的亚光刻孔。

23. 发明授权

US07368712B2 Y-shaped carbon nanotubes as AFM probe for analyzing substrates with angled topography 有权
标题翻译： Y型碳纳米管作为用于分析具有倾斜的地形的基底的AFM探针
公开(公告)号：US07368712B2
公开(公告)日：2008-05-06
申请号：US11164792
申请日：2005-12-06
申请人： Carol A. Boye , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Carol A. Boye , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： G01N23/00 , G21K7/00
CPC分类号： G01Q60/42 , G01Q70/12
摘要： A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the chemically modified carbon nanotube is modified with any of an amine, carboxyl, fluorine, and metallic component. Preferably, each of the pair of angled arms comprises a length of at least 200 nm and a diameter between 10 and 200 nm. Moreover, the chemically modified carbon nanotube is preferably adapted to allow differentiation between substrate materials to be probed. Additionally, the chemically modified carbon nanotube is preferably adapted to allow fluorine gas to flow through the chemically modified carbon nanotube onto a substrate to be characterized. Furthermore, the chemically modified carbon nanotube is preferably adapted to chemically react with a substrate surface to be characterized.
摘要翻译： Y型碳纳米管原子力显微镜探针头和方法包括轴部分; 一对成角度的臂，其从所述轴部的同一端延伸，其中所述轴部和所述一对成角度的臂包括化学改性的碳纳米管，并且其中所述化学改性的碳纳米管用胺，羧基，氟，和金属成分。优选地，一对成角度的臂中的每一个包括至少200nm的长度和10和200nm之间的直径。此外，化学改性的碳纳米管优选适于允许待探测的基底材料之间的分化。此外，化学改性的碳纳米管优选适于使氟气通过化学改性的碳纳米管流动到待表征的基底上。此外，化学改性的碳纳米管优选适于与要表征的基材表面发生化学反应。

24. 发明授权

US07358140B2 Pattern density control using edge printing processes 有权
标题翻译：图案密度控制采用边缘印刷工艺
公开(公告)号：US07358140B2
公开(公告)日：2008-04-15
申请号：US11163968
申请日：2005-11-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L27/1052 , Y10S438/95
摘要： A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of the M design normal regions, wherein N is a positive integer. Next, an actual structure is provided that includes (i) an actual substrate corresponding to the design substrate, (ii) a to-be-etched layer on the actual substrate, and (iii) a memory layer on the to-be-etched layer. Next, an edge printing process is performed on the memory layer so as to form (a) M normal memory portions aligned with the M design normal regions and (b) N sacrificial memory portions aligned with the N design sacrificial regions.
摘要翻译：一种结构制造方法。该方法包括提供一种设计结构，其包括（i）设计基板和（ii）设计基板上的M设计法线区域，其中M是大于1的正整数。接下来，在两个相邻设计之间添加N个设计牺牲区域 M正常区域的正常区域，其中N是正整数。接下来，提供实际结构，其包括（i）与设计基板对应的实际基板，（ii）实际基板上的待蚀刻层，以及（iii）待蚀刻的存储层层。接下来，对存储层执行边缘打印处理，以便形成（a）与M设计法线区域对准的M个正常存储器部分和（b）与N个设计牺牲区域对准的N个牺牲存储器部分。

25. 发明授权

US07351648B2 Methods for forming uniform lithographic features 有权
标题翻译：形成均匀光刻特征的方法
公开(公告)号：US07351648B2
公开(公告)日：2008-04-01
申请号：US11335372
申请日：2006-01-19
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Chung Hon Lam
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Chung Hon Lam
IPC分类号： H01L21/44 , H01L21/76
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76885
摘要： Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the overhang and in the holes until the conformal layer closes off the holes to form a void/seam in each hole. The void/seam in each hole is exposed by etching back a top surface. The void/seam in each hole is extended to the underlying layer.
摘要翻译：制造半导体器件的方法包括在下层上形成第一层，在第一层上形成硬掩模，以及通过硬掩模和第一层图形化孔。形成在孔的侧面上延伸的突出端。保形层沉积在悬垂孔和孔中，直到共形层封闭孔，以在每个孔中形成空隙/接缝。每个孔中的空隙/接缝通过蚀刻顶部表面而暴露出来。每个孔中的空隙/接缝延伸到下层。

26. 发明授权

US07348610B2 Multiple layer and crystal plane orientation semiconductor substrate 有权
标题翻译：多层和晶面取向半导体衬底
公开(公告)号：US07348610B2
公开(公告)日：2008-03-25
申请号：US10906557
申请日：2005-02-24
申请人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Leathen Shi, III
发明人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Leathen Shi, III
IPC分类号： H01L27/10
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
摘要翻译：绝缘体上半导体衬底及其制造方法。所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向，第一晶体方向与第二晶体方向不同。

27. 发明授权

US07345370B2 Wiring patterns formed by selective metal plating 有权
标题翻译：通过选择性金属电镀形成的布线图案
公开(公告)号：US07345370B2
公开(公告)日：2008-03-18
申请号：US10905590
申请日：2005-01-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L23/48
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/7682 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76871 , H01L21/76874 , H01L23/5283 , H01L23/53209 , H01L2221/1089 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.
摘要翻译：使用图案结构（心轴）并激活结构的侧壁的方法形成导电侧壁间隔结构。金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

28. 发明授权

US07329613B2 Structure and method for forming semiconductor wiring levels using atomic layer deposition 失效
标题翻译：使用原子层沉积形成半导体布线层的结构和方法
公开(公告)号：US07329613B2
公开(公告)日：2008-02-12
申请号：US10906899
申请日：2005-03-11
申请人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76885 , C23C16/045 , H01L21/28562 , H01L21/76852 , H01L23/53209 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a conductive wire structure for a semiconductor device includes defining a mandrel on a substrate, forming a conductive wire material on the mandrel by atomic layer deposition, and forming a liner material around the conductive wire material by atomic layer deposition.
摘要翻译：一种用于形成半导体器件的导线结构的方法包括在基片上限定心轴，通过原子层沉积在心轴上形成导线材料，并通过原子层沉积在导线材料周围形成衬垫材料。

29. 发明授权

US07265013B2 Sidewall image transfer (SIT) technologies 失效
标题翻译：侧墙图像传输（SIT）技术
公开(公告)号：US07265013B2
公开(公告)日：2007-09-04
申请号：US11162662
申请日：2005-09-19
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Kirk D. Peterson
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Kirk D. Peterson
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132
摘要： A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.
摘要翻译：一种结构制造方法。该方法包括提供一种结构，该结构包括：（a）待蚀刻层，（b）存储区域，（c）位于彼此顶部的定位区域（d）和封盖区域。然后，定位区域缩进。然后，在结构的暴露于环境的表面上形成保形层。然后，去除保形层的一部分，以将覆盖区域暴露于周围环境，而不会使存储区域暴露于周围环境。然后，去除封盖区域，以将定位区域暴露于周围环境。然后，移除定位区域，以将存储区域暴露于周围环境。然后，存储区域被定向蚀刻，保形层的剩余部分用作阻挡掩模。

30. 发明授权

US06503813B1 Method and structure for forming a trench in a semiconductor substrate 有权
标题翻译：在半导体衬底中形成沟槽的方法和结构
公开(公告)号：US06503813B1
公开(公告)日：2003-01-07
申请号：US09595978
申请日：2000-06-16
申请人： Charles W. Koburger, III
发明人： Charles W. Koburger, III
IPC分类号： H01L2176
CPC分类号： H01L21/763 , H01L21/3081 , H01L27/1087
摘要： A method and structure for forming a trench in a semiconductor substrate that includes a semiconductor material such as silicon. The method and structure may be used to form a deep trench or a shallow trench, without having a pad oxide in contact with the semiconductor substrate. The method for forming the deep trench forms a nitride layer on the semiconductor substrate, wherein the selectively etchable layer (e.g., a nitride layer) is selectively etchable with respect to the semiconductor substrate, and wherein there is no pad oxide between the selectively etchable layer and the semiconductor substrate. An erosion resistant layer (e.g., a hard mask oxide layer) is formed on the selectively etchable layer, wherein the erosion resistant layer is resistant to being etched by a reactive ion etch (RIE) process that etches the semiconductor substrate. Then the deep trench is formed by RIE through the erosion resistant layer, through the selectively etchable layer, and into the semiconductor substrate. The method for forming the shallow trench forms a nitride layer on the semiconductor substrate, wherein the selectively etchable layer (e.g., a nitride layer) is selectively etchable with respect to the semiconductor substrate, and wherein there is no pad oxide between the selectively etchable layer and the semiconductor substrate. Then the deep trench is formed by RIE through the selectively etchable layer and into the semiconductor substrate, followed by depositing and planarizing an insulative material in the shallow trench.
摘要翻译：一种用于在半导体衬底中形成沟槽的方法和结构，其包括半导体材料如硅。该方法和结构可用于形成深沟槽或浅沟槽，而不会使衬垫氧化物与半导体衬底接触。用于形成深沟槽的方法在半导体衬底上形成氮化物层，其中可选择的可蚀刻层（例如，氮化物层）可相对于半导体衬底选择性地蚀刻，并且其中在该可选择性蚀刻层和半导体衬底。在可选择的可蚀刻层上形成耐腐蚀层（例如，硬掩模氧化物层），其中抗腐蚀层耐腐蚀半导体衬底的反应离子蚀刻（RIE）工艺蚀刻。然后，深沟通过RIE通过耐腐蚀层，通过选择性可蚀刻层形成并进入半导体衬底。用于形成浅沟槽的方法在半导体衬底上形成氮化物层，其中可选择的可蚀刻层（例如，氮化物层）可相对于半导体衬底选择性地蚀刻，并且其中在该可选择性蚀刻层和半导体衬底。然后，深沟槽通过RIE通过选择性可蚀刻层形成并进入半导体衬底，然后沉积并平坦化浅沟槽中的绝缘材料。

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