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1. 发明授权

US07351648B2 Methods for forming uniform lithographic features 有权
标题翻译：形成均匀光刻特征的方法
公开(公告)号：US07351648B2
公开(公告)日：2008-04-01
申请号：US11335372
申请日：2006-01-19
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Chung Hon Lam
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Chung Hon Lam
IPC分类号： H01L21/44 , H01L21/76
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76885
摘要： Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the overhang and in the holes until the conformal layer closes off the holes to form a void/seam in each hole. The void/seam in each hole is exposed by etching back a top surface. The void/seam in each hole is extended to the underlying layer.
摘要翻译：制造半导体器件的方法包括在下层上形成第一层，在第一层上形成硬掩模，以及通过硬掩模和第一层图形化孔。形成在孔的侧面上延伸的突出端。保形层沉积在悬垂孔和孔中，直到共形层封闭孔，以在每个孔中形成空隙/接缝。每个孔中的空隙/接缝通过蚀刻顶部表面而暴露出来。每个孔中的空隙/接缝延伸到下层。

2. 发明授权

US07932167B2 Phase change memory cell with vertical transistor 有权
标题翻译：具有垂直晶体管的相变存储单元
公开(公告)号：US07932167B2
公开(公告)日：2011-04-26
申请号：US11771457
申请日：2007-06-29
申请人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
发明人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
IPC分类号： H01L21/44
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1683
摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.
摘要翻译：部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。岛形成在下电极特征上并具有一个或多个侧壁。它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

3. 发明申请

US20090001337A1 Phase Change Memory Cell with Vertical Transistor 有权
标题翻译：具有垂直晶体管的相变存储单元
公开(公告)号：US20090001337A1
公开(公告)日：2009-01-01
申请号：US11771457
申请日：2007-06-29
申请人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
发明人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
IPC分类号： H01L21/336 , H01L21/06 , H01L29/02
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1683
摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.
摘要翻译：部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。岛形成在下电极特征上并具有一个或多个侧壁。它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

4. 发明申请

US20080142995A1 LAYOUT AND PROCESS TO CONTACT SUB-LITHOGRAPHIC STRUCTURES 有权
标题翻译：布局和过程联系次地层结构
公开(公告)号：US20080142995A1
公开(公告)日：2008-06-19
申请号：US12034901
申请日：2008-02-21
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger , Chung Hon Lam
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger , Chung Hon Lam
IPC分类号： H01L23/48
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/76885 , H01L21/76895 , H01L23/528 , H01L2224/06 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.
摘要翻译：一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。第一和第二结构被嵌套，使得亚光刻线以平行的方式设置在宽度内，并且第一结构的接触着陆段设置在相对于子平版印刷线的相对侧第二结构的接触着陆段。用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。

5. 发明授权

US07351666B2 Layout and process to contact sub-lithographic structures 有权
标题翻译：接触亚光刻结构的布局和工艺
公开(公告)号：US07351666B2
公开(公告)日：2008-04-01
申请号：US11378492
申请日：2006-03-17
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/76885 , H01L21/76895 , H01L23/528 , H01L2224/06 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.
摘要翻译：一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。第一和第二结构被嵌套，使得亚光刻线以平行方式设置在宽度内，并且第一结构的接触着陆段被设置在相对于子平版印刷线的相对侧的相对侧第二结构的接触着陆段。用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。

6. 发明授权

US07825525B2 Layout and process to contact sub-lithographic structures 有权
标题翻译：接触亚光刻结构的布局和工艺
公开(公告)号：US07825525B2
公开(公告)日：2010-11-02
申请号：US12034901
申请日：2008-02-21
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
IPC分类号： H01L23/48
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/76885 , H01L21/76895 , H01L23/528 , H01L2224/06 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.
摘要翻译：一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。第一和第二结构被嵌套，使得亚光刻线以平行的方式设置在宽度内，并且第一结构的接触着陆段被设置在相对于子平版印刷线的长度相对侧第二结构的接触着陆段。用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。

7. 发明授权

US06326275B1 DRAM cell with vertical CMOS transistor 有权
标题翻译：具有垂直CMOS晶体管的DRAM单元
公开(公告)号：US06326275B1
公开(公告)日：2001-12-04
申请号：US09559363
申请日：2000-04-24
申请人： Jay G. Harrington , David V. Horak , Kevin M. Houlihan , Chung Hon Lam , Rebecca D. Mih
发明人： Jay G. Harrington , David V. Horak , Kevin M. Houlihan , Chung Hon Lam , Rebecca D. Mih
IPC分类号： H01L2120
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A DRAM memory cell having a trench capacitor includes a vertical pass transistor formed in the top of the trench in a process that forms a doped poly protective layer on the upper sidewalls above a sacrificial intrinsic poly spacer layer, the doped poly protecting the sidewalls while the intrinsic poly spacer layer is removed and replaced with a conductive strap layer that both forms a strap from the capacitor electrode and serves as a source of dopant to form a transistor electrode in the silicon substrate; the protective layer and the upper portion of the strap material being removed simultaneously so that no extra step is required; after which the trench walls are oxidized to form the transistor gate dielectric and conductive material is deposited to form the wordline and the gates for the vertical transistors simultaneously.
摘要翻译：具有沟槽电容器的DRAM存储单元包括形成在沟槽顶部的垂直传输晶体管，该工艺在牺牲本征聚间隔层上方的上侧壁上形成掺杂的多晶保护层，掺杂的多晶硅保护侧壁，而本征聚间隔层被去除并被导电带层替代，导电带层都形成来自电容器电极的带，并且用作掺杂剂源以在硅衬底中形成晶体管电极; 保护层和带材的上部被同时移除，使得不需要额外的步骤; 之后，沟槽壁被氧化以形成晶体管栅极电介质并且沉积导电材料以同时形成用于垂直晶体管的字线和栅极。

8. 发明授权

US08445313B2 Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process 失效
标题翻译：用于形成PCRAM和自对准回蚀工艺的自对准位线的方法
公开(公告)号：US08445313B2
公开(公告)日：2013-05-21
申请号：US13546684
申请日：2012-07-11
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译：一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有上表面与牺牲材料的基座的上表面基本共面。牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。还提供了自对准的回蚀工艺。

9. 发明申请

US20120202333A1 METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS 有权
标题翻译：用于形成用于PCRAM和自对准回退过程的自对准位线的方法
公开(公告)号：US20120202333A1
公开(公告)日：2012-08-09
申请号：US13020051
申请日：2011-02-03
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/02
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译：一种形成与相变材料对准的位线的方法，其包括在下电极的一部分上形成牺牲材料的基座并且与邻近所述牺牲材料的至少一个电介质材料相连，其中所述至少一种电介质材料具有上表面与牺牲材料的基座的上表面基本共面。牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。还提供了自对准的回蚀工艺。

10. 发明授权

US08238149B2 Methods and apparatus for reducing defect bits in phase change memory 有权
标题翻译：用于减少相变存储器中缺陷位的方法和装置
公开(公告)号：US08238149B2
公开(公告)日：2012-08-07
申请号：US12715802
申请日：2010-03-02
申请人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

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