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21. 发明申请

US20090218610A1 Semiconductor Memory Devices Including Diagonal Bit Lines 有权
标题翻译：包括对角位线的半导体存储器件
公开(公告)号：US20090218610A1
公开(公告)日：2009-09-03
申请号：US12465234
申请日：2009-05-13
申请人： Don-Hoon Goo , Han-Ku Cho , Joo-Tac Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Don-Hoon Goo , Han-Ku Cho , Joo-Tac Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10882 , H01L27/11502
摘要： A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns.
摘要翻译：半导体存储器件可以包括具有多个有源区的半导体衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。长度可以大于宽度，并且多个有源区域可以在第二轴线的方向上以多个列设置。可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。衬底上的多个位线可以跨越多个字线对，每个位线电耦合到每列的相应有源区的漏极部分，并且每个位线在不同方向上与相邻列的有源区域的漏极部分交叉使得相同位线的不同部分在相邻列的不同有效区域上在不同方向上对准。

22. 发明申请

US20060099538A1 Methods of performing a photolithography process for forming asymmetric patterns and methods of forming a semiconductor device using the same 有权
公开(公告)号：US20060099538A1
公开(公告)日：2006-05-11
申请号：US11230957
申请日：2005-09-20
申请人： Joon-Soo Park , Gi-Sung Yeo , Han-Ku Cho , Sang-Gyun Woo , Tae-Young Kim , Byeong-Soo Kim
发明人： Joon-Soo Park , Gi-Sung Yeo , Han-Ku Cho , Sang-Gyun Woo , Tae-Young Kim , Byeong-Soo Kim
IPC分类号： G03F7/00
CPC分类号： G03F7/2022 , G03F1/70 , G03F7/203 , G03F7/70466 , G03F7/705
摘要： There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer. An etching process is performed on the planarized insulating interlayer to expose the semiconductor substrate, using the first photoresist pattern and the second photoresist pattern as etch masks.

23. 发明申请

US20060073396A1 Multi-exposure semiconductor fabrication mask sets and methods of fabricating such multi-exposure mask sets 有权
公开(公告)号：US20060073396A1
公开(公告)日：2006-04-06
申请号：US11243401
申请日：2005-10-04
申请人： Doo-Youl Lee , Seok-Hwan Oh , Gi-Sung Yeo , Sang-Gyun Woo , Sook Lee , Joo-On Park , Sung-Gon Jung
发明人： Doo-Youl Lee , Seok-Hwan Oh , Gi-Sung Yeo , Sang-Gyun Woo , Sook Lee , Joo-On Park , Sung-Gon Jung
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F7/70466 , G03F1/00
摘要： Mask sets are provided which may be used to define a first pattern region that has a first pitch pattern and a second pattern region that has a second pitch pattern during the fabrication of a semiconductor device. These mask sets may include a first mask that has a first exposure region in which a first halftone pattern defines the first pattern region and a first screen region in which a first shield layer covers the second pattern region. These mask sets may further include a second mask that has a second exposure region in which a second halftone pattern defines the second pattern region and a second screen region in which a second shield layer covers the first pattern region. The second shield layer also extends from the second screen region to cover a portion of the second halftone pattern.

24. 发明申请

US20100190303A1 Semiconductor device having sufficient process margin and method of forming same 有权
标题翻译：具有足够的加工余量的半导体器件及其形成方法
公开(公告)号：US20100190303A1
公开(公告)日：2010-07-29
申请号：US12654798
申请日：2010-01-04
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： H01L21/8239
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

25. 发明授权

US06537713B2 Multilayer alignment keys and alignment method using the same 有权
标题翻译：多层对齐键和对齐方法使用相同
公开(公告)号：US06537713B2
公开(公告)日：2003-03-25
申请号：US09761618
申请日：2001-01-16
申请人： Gi-Sung Yeo
发明人： Gi-Sung Yeo
IPC分类号： G03F900
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Multilayer alignment keys in an integrated structure and a method of aligning using the keys are provided. Alignment keys are formed on a semiconductor substrate in a multilayer structure. The length of the alignment key in one layer can be different from that of the alignment key in underlying and/or overlying layer. Alternatively, the number of alignment keys can be different in each layer. Thus alignment weight can be imposed differently on each layer, thereby increasing alignment accuracy.
摘要翻译：提供了一体化结构中的多层对齐键和使用键对准的方法。在多层结构中的半导体衬底上形成对准键。一层中对齐键的长度可能与底层和/或上覆层中的对齐键的长度不同。或者，对准键的数量可以在每个层中不同。因此，可以在每层上施加不同的对准重量，从而提高对准精度。

26. 发明授权

US07176512B2 Semiconductor memory device having high electrical performance and mask and photolithography friendliness 有权
标题翻译：具有高电气性能和掩模和光刻友好性的半导体存储器件
公开(公告)号：US07176512B2
公开(公告)日：2007-02-13
申请号：US10918175
申请日：2004-08-13
申请人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
发明人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10891
摘要： A semiconductor memory device comprises a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.
摘要翻译：半导体存储器件包括多行，每行包括以间距排列的多个有源区，其中相邻行中的有源区相对于间距彼此偏移一半，其中每个有源区之间的距离在一行中等于相邻行中的活动区域之间的距离。

27. 发明授权

US07001697B2 Photomask having a transparency-adjusting layer, method of manufacturing the photomask, and exposure method using the photomask 有权
标题翻译：具有透明度调节层的光掩模，光掩模的制造方法和使用光掩模的曝光方法
公开(公告)号：US07001697B2
公开(公告)日：2006-02-21
申请号：US10623616
申请日：2003-07-22
申请人： Jong-Rak Park , Seong-Woon Choi , Gi-Sung Yeo , Sung-Hoon Jang
发明人： Jong-Rak Park , Seong-Woon Choi , Gi-Sung Yeo , Sung-Hoon Jang
IPC分类号： G01F9/00
CPC分类号： G02B27/0927 , G02B5/1871 , G02B27/09 , G02B27/0938 , G02B27/46 , G03F1/50 , G03F7/70191
摘要： A photomask for use in photolithography has substrate, a main pattern at one side of the substrate, and a transparency-adjusting layer at the other side of the substrate. The transparency-adjusting layer has a characteristic that allows it to change the intensity of the illumination incident on the main pattern during the exposure process accordingly. In manufacturing the photomask, a first exposure process is carried out on a wafer using just the substrate and main pattern. The critical dimensions of elements of the pattern formed on the wafer as a result of the first exposure process are measured. Differences between these critical dimensions and a reference critical dimension are then used in designing a layout of the transparency-adjusting layer in which the characteristic of the layer is varied to compensate for such differences.
摘要翻译：用于光刻的光掩模具有衬底，衬底一侧的主图案和衬底另一侧的透明度调节层。透明度调整层具有允许其在曝光处理期间改变在主图案上入射的照明强度的特性。在制造光掩模时，仅使用基板和主图案在晶片上进行第一曝光处理。测量作为第一曝光处理的结果在晶片上形成的图案的元件的临界尺寸。然后在设计透明度调整层的布局时，将这些关键尺寸与参考临界尺寸之间的差异用于改变层的特性以补偿这种差异。

28. 发明申请

US20050070080A1 Method of forming self-aligned contact pads of non-straight type semiconductor memory device 有权
标题翻译：形成非直型半导体存储器件的自对准接触焊盘的方法
公开(公告)号：US20050070080A1
公开(公告)日：2005-03-31
申请号：US10944151
申请日：2004-09-16
申请人： Eun-Mi Lee , Doo-Hoon Goo , Jung-Hyeon Lee , Gi-Sung Yeo
发明人： Eun-Mi Lee , Doo-Hoon Goo , Jung-Hyeon Lee , Gi-Sung Yeo
IPC分类号： H01L21/28 , H01L21/4763 , H01L21/60 , H01L23/485
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.
摘要翻译：本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。然后，可以在层间绝缘层上形成光致抗蚀剂层。可以通过使用具有例如棒型，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光致抗蚀剂图案。然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。然后可以通过用导电材料填充接触孔来形成接触垫。

29. 发明申请

US20050012157A1 Semiconductor device having sufficient process margin and method of forming same 有权
标题翻译：具有足够的加工余量的半导体器件及其形成方法
公开(公告)号：US20050012157A1
公开(公告)日：2005-01-20
申请号：US10892588
申请日：2004-07-15
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： G11C11/34 , G11C11/412 , H01L27/02 , H01L27/11
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

30. 发明授权

US08193047B2 Semiconductor device having sufficient process margin and method of forming same 有权
标题翻译：具有足够的加工余量的半导体器件及其形成方法
公开(公告)号：US08193047B2
公开(公告)日：2012-06-05
申请号：US12654798
申请日：2010-01-04
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： H01L21/8239
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

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