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1. 发明申请

US20050070080A1 Method of forming self-aligned contact pads of non-straight type semiconductor memory device 有权
标题翻译：形成非直型半导体存储器件的自对准接触焊盘的方法
公开(公告)号：US20050070080A1
公开(公告)日：2005-03-31
申请号：US10944151
申请日：2004-09-16
申请人： Eun-Mi Lee , Doo-Hoon Goo , Jung-Hyeon Lee , Gi-Sung Yeo
发明人： Eun-Mi Lee , Doo-Hoon Goo , Jung-Hyeon Lee , Gi-Sung Yeo
IPC分类号： H01L21/28 , H01L21/4763 , H01L21/60 , H01L23/485
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.
摘要翻译：本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。然后，可以在层间绝缘层上形成光致抗蚀剂层。可以通过使用具有例如棒型，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光致抗蚀剂图案。然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。然后可以通过用导电材料填充接触孔来形成接触垫。

2. 发明授权

US07064051B2 Method of forming self-aligned contact pads of non-straight type semiconductor memory device 有权
标题翻译：形成非直型半导体存储器件的自对准接触焊盘的方法
公开(公告)号：US07064051B2
公开(公告)日：2006-06-20
申请号：US10944151
申请日：2004-09-16
申请人： Eun-Mi Lee , Doo-Hoon Goo , Jung-Hyeon Lee , Gi-Sung Yeo
发明人： Eun-Mi Lee , Doo-Hoon Goo , Jung-Hyeon Lee , Gi-Sung Yeo
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.
摘要翻译：本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。然后，可以在层间绝缘层上形成光致抗蚀剂层。可以通过使用具有例如条形，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光刻胶图案。然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。然后可以通过用导电材料填充接触孔来形成接触垫。

3. 发明授权

US07375390B2 Semiconductor memory device having high electrical performance and mask and photolithography friendliness 有权
标题翻译：具有高电气性能和掩模和光刻友好性的半导体存储器件
公开(公告)号：US07375390B2
公开(公告)日：2008-05-20
申请号：US11621617
申请日：2007-01-10
申请人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
发明人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10891
摘要： A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.
摘要翻译：半导体存储器件包括多行，每行包括以间距排列的多个有源区，其中相邻行中的有源区相对于间距彼此偏移一半，其中每个有源区之间的距离在一行中等于相邻行中的活动区域之间的距离。

4. 发明申请

US20050035387A1 Semiconductor memory device having high electrical performance and mask and photolithography friendliness 有权
标题翻译：具有高电气性能和掩模和光刻友好性的半导体存储器件
公开(公告)号：US20050035387A1
公开(公告)日：2005-02-17
申请号：US10918175
申请日：2004-08-13
申请人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
发明人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
IPC分类号： H01L27/04 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10891
摘要： A semiconductor memory device comprises a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.
摘要翻译：半导体存储器件包括多行，每行包括以间距排列的多个有源区，其中相邻行中的有源区相对于间距彼此偏移一半，其中每个有源区之间的距离在一行中等于相邻行中的活动区域之间的距离。

5. 发明授权

US07176512B2 Semiconductor memory device having high electrical performance and mask and photolithography friendliness 有权
标题翻译：具有高电气性能和掩模和光刻友好性的半导体存储器件
公开(公告)号：US07176512B2
公开(公告)日：2007-02-13
申请号：US10918175
申请日：2004-08-13
申请人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
发明人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10891
摘要： A semiconductor memory device comprises a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.
摘要翻译：半导体存储器件包括多行，每行包括以间距排列的多个有源区，其中相邻行中的有源区相对于间距彼此偏移一半，其中每个有源区之间的距离在一行中等于相邻行中的活动区域之间的距离。

6. 发明申请

US20070108491A1 SEMICONDUCTOR MEMORY DEVICE HAVING HIGH ELECTRICAL PERFORMANCE AND MASK AND PHOTOLITHOGRAPHY FRIENDLINESS 有权
标题翻译：具有高电气性能和掩模和图像友情的半导体存储器件
公开(公告)号：US20070108491A1
公开(公告)日：2007-05-17
申请号：US11621617
申请日：2007-01-10
申请人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
发明人： Jung-Hyeon Lee , Gi-Sung Yeo , Doo-Hoon Goo , Woo-Sung Han
IPC分类号： H01L29/94
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10891
摘要： A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.
摘要翻译：半导体存储器件包括多行，每行包括以间距排列的多个有源区，其中相邻行中的有源区相对于间距彼此偏移一半，其中每个有源区之间的距离在一行中等于相邻行中的活动区域之间的距离。

7. 发明申请

US20090218609A1 Semiconductor Memory Devices Including Offset Bit Lines 有权
标题翻译：包括偏移位线的半导体存储器件
公开(公告)号：US20090218609A1
公开(公告)日：2009-09-03
申请号：US12465202
申请日：2009-05-13
申请人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10882 , H01L27/11502
摘要： A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.
摘要翻译：半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间相同列的相邻有效区域。

8. 发明申请

US20060076599A1 Semiconductor memory devices including offset active regions 有权
公开(公告)号：US20060076599A1
公开(公告)日：2006-04-13
申请号：US11246594
申请日：2005-10-06
申请人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L27/11502 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10855
摘要： A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.

9. 发明授权

US08013374B2 Semiconductor memory devices including offset bit lines 有权
标题翻译：包括偏移位线的半导体存储器件
公开(公告)号：US08013374B2
公开(公告)日：2011-09-06
申请号：US12465202
申请日：2009-05-13
申请人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10882 , H01L27/11502
摘要： A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.
摘要翻译：半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间相同列的相邻有效区域。

10. 发明授权

US07547936B2 Semiconductor memory devices including offset active regions 有权
标题翻译：包括偏移活动区域的半导体存储器件
公开(公告)号：US07547936B2
公开(公告)日：2009-06-16
申请号：US11246594
申请日：2005-10-06
申请人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L271/108
CPC分类号： H01L27/11502 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10855
摘要： A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.
摘要翻译：半导体存储器件可以包括具有多个有源区的衬底和围绕衬底的有源区的衬底上的场隔离层。多个有源区域中的每一个可以具有在第一轴线的方向上的长度和在第二轴线的方向上的宽度，并且该长度可以大于宽度。多个有源区域可以沿着第二轴线的方向设置在多个活性区域列中，并且相邻列的有效区域可以在第二轴线的方向上偏移。

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