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1. 发明授权

US07550383B2 Methods of performing a photolithography process for forming asymmetric patterns and methods of forming a semiconductor device using the same 有权
标题翻译：执行用于形成不对称图案的光刻工艺的方法和使用其形成半导体器件的方法
公开(公告)号：US07550383B2
公开(公告)日：2009-06-23
申请号：US11230957
申请日：2005-09-20
申请人： Joon-Soo Park , Gi-Sung Yeo , Han-Ku Cho , Sang-Gyun Woo , Tae-Young Kim , Byeong-Soo Kim
发明人： Joon-Soo Park , Gi-Sung Yeo , Han-Ku Cho , Sang-Gyun Woo , Tae-Young Kim , Byeong-Soo Kim
IPC分类号： H01L21/44 , H01L21/00
CPC分类号： G03F7/2022 , G03F1/70 , G03F7/203 , G03F7/70466 , G03F7/705
摘要： There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer. An etching process is performed on the planarized insulating interlayer to expose the semiconductor substrate, using the first photoresist pattern and the second photoresist pattern as etch masks.
摘要翻译：提供了用于形成不对称半导体图案的光刻工艺的方法和使用其形成半导体器件的方法。这些方法提供了通过两个曝光工艺在光致抗蚀剂层上形成不对称半导体图案的方法。为此，制备半导体衬底。在半导体基板的整个表面上依次形成平坦化的绝缘中间层和光致抗蚀剂层。将光刻掩模的第一半导体图案转印到光致抗蚀剂层，从而在光致抗蚀剂层上形成光致抗蚀剂图案。第二光刻掩模的第二半导体图案被连续转印到光致抗蚀剂层，从而在光致抗蚀剂层上形成第二光致抗蚀剂图案。在平坦化的绝缘中间层上进行蚀刻处理，以使用第一光致抗蚀剂图案和第二光致抗蚀剂图案作为蚀刻掩模来暴露半导体衬底。

2. 发明申请

US20060099538A1 Methods of performing a photolithography process for forming asymmetric patterns and methods of forming a semiconductor device using the same 有权
公开(公告)号：US20060099538A1
公开(公告)日：2006-05-11
申请号：US11230957
申请日：2005-09-20
申请人： Joon-Soo Park , Gi-Sung Yeo , Han-Ku Cho , Sang-Gyun Woo , Tae-Young Kim , Byeong-Soo Kim
发明人： Joon-Soo Park , Gi-Sung Yeo , Han-Ku Cho , Sang-Gyun Woo , Tae-Young Kim , Byeong-Soo Kim
IPC分类号： G03F7/00
CPC分类号： G03F7/2022 , G03F1/70 , G03F7/203 , G03F7/70466 , G03F7/705
摘要： There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer. An etching process is performed on the planarized insulating interlayer to expose the semiconductor substrate, using the first photoresist pattern and the second photoresist pattern as etch masks.

3. 发明授权

US08013375B2 Semiconductor memory devices including diagonal bit lines 有权
标题翻译：半导体存储器件包括对角位线
公开(公告)号：US08013375B2
公开(公告)日：2011-09-06
申请号：US12465234
申请日：2009-05-13
申请人： Duo-Hoon Goo , Han-Ku Cho , Joo-Tac Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Duo-Hoon Goo , Han-Ku Cho , Joo-Tac Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10882 , H01L27/11502
摘要： A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns.
摘要翻译：半导体存储器件可以包括具有多个有源区的半导体衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。长度可以大于宽度，并且多个有源区域可以在第二轴线的方向上以多个列设置。可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。衬底上的多个位线可以跨越多个字线对，每个位线电耦合到每列的相应有源区的漏极部分，并且每个位线在不同方向上与相邻列的有源区域的漏极部分交叉使得相同位线的不同部分在相邻列的不同有效区域上在不同方向上对准。

4. 发明申请

US20090218654A1 Semiconductor Memory Devices Including Extended Memory Elements 审中-公开
标题翻译：包括扩展内存元素的半导体存储器件
公开(公告)号：US20090218654A1
公开(公告)日：2009-09-03
申请号：US12465261
申请日：2009-05-13
申请人： Don-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Don-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L29/06 , H01L29/68
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10882 , H01L27/11502
摘要： A semiconductor memory device may include a semiconductor substrate having an active region thereof, and the active region may have a length and a width, with the length being greater than the width. A field isolation layer may be on the semiconductor substrate surrounding the active region. First and second wordlines may be on the substrate crossing the active region, with the first and second wordlines defining a drain portion of the active region between the first and second wordlines and first and second source portions of the active region at opposite ends of the active region. First and second memory storage elements may be respectively coupled to the first and second source portions of the active region, with the first and second wordlines being between portions of the respective first and second memory storage elements and the active region in a direction perpendicular to a surface of the substrate.
摘要翻译：半导体存储器件可以包括具有其有源区的半导体衬底，并且有源区可以具有长度和宽度，其长度大于宽度。场隔离层可以在围绕有源区的半导体衬底上。第一和第二字线可以在与有源区交叉的衬底上，其中第一和第二字线限定在第一和第二字线之间的有源区的漏极部分和有源区的第一和第二源极部分在有源区域的相对端处地区。第一和第二存储器存储元件可以分别耦合到有源区域的第一和第二源极部分，其中第一和第二字线在相应的第一和第二存储器存储元件的部分之间，并且有源区域在垂直于基板的表面。

5. 发明申请

US20090218609A1 Semiconductor Memory Devices Including Offset Bit Lines 有权
标题翻译：包括偏移位线的半导体存储器件
公开(公告)号：US20090218609A1
公开(公告)日：2009-09-03
申请号：US12465202
申请日：2009-05-13
申请人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10882 , H01L27/11502
摘要： A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.
摘要翻译：半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间相同列的相邻有效区域。

6. 发明授权

US07547936B2 Semiconductor memory devices including offset active regions 有权
标题翻译：包括偏移活动区域的半导体存储器件
公开(公告)号：US07547936B2
公开(公告)日：2009-06-16
申请号：US11246594
申请日：2005-10-06
申请人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L271/108
CPC分类号： H01L27/11502 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10855
摘要： A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.
摘要翻译：半导体存储器件可以包括具有多个有源区的衬底和围绕衬底的有源区的衬底上的场隔离层。多个有源区域中的每一个可以具有在第一轴线的方向上的长度和在第二轴线的方向上的宽度，并且该长度可以大于宽度。多个有源区域可以沿着第二轴线的方向设置在多个活性区域列中，并且相邻列的有效区域可以在第二轴线的方向上偏移。

7. 发明申请

US20060076599A1 Semiconductor memory devices including offset active regions 有权
公开(公告)号：US20060076599A1
公开(公告)日：2006-04-13
申请号：US11246594
申请日：2005-10-06
申请人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L27/11502 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10855
摘要： A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.

8. 发明授权

US08013374B2 Semiconductor memory devices including offset bit lines 有权
标题翻译：包括偏移位线的半导体存储器件
公开(公告)号：US08013374B2
公开(公告)日：2011-09-06
申请号：US12465202
申请日：2009-05-13
申请人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10882 , H01L27/11502
摘要： A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.
摘要翻译：半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间相同列的相邻有效区域。

9. 发明申请

US20090218610A1 Semiconductor Memory Devices Including Diagonal Bit Lines 有权
标题翻译：包括对角位线的半导体存储器件
公开(公告)号：US20090218610A1
公开(公告)日：2009-09-03
申请号：US12465234
申请日：2009-05-13
申请人： Don-Hoon Goo , Han-Ku Cho , Joo-Tac Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Don-Hoon Goo , Han-Ku Cho , Joo-Tac Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10882 , H01L27/11502
摘要： A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns.
摘要翻译：半导体存储器件可以包括具有多个有源区的半导体衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。长度可以大于宽度，并且多个有源区域可以在第二轴线的方向上以多个列设置。可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。衬底上的多个位线可以跨越多个字线对，每个位线电耦合到每列的相应有源区的漏极部分，并且每个位线在不同方向上与相邻列的有源区域的漏极部分交叉使得相同位线的不同部分在相邻列的不同有效区域上在不同方向上对准。

10. 发明申请

US20080097729A1 Method of manufacturing mask 失效
标题翻译：制作面膜的方法
公开(公告)号：US20080097729A1
公开(公告)日：2008-04-24
申请号：US11590244
申请日：2006-10-31
申请人： Sung-Gon Jung , Gi-Sung Yeo , Young-Mi Lee , Han-Ku Cho
发明人： Sung-Gon Jung , Gi-Sung Yeo , Young-Mi Lee , Han-Ku Cho
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F1/36
摘要： A method of manufacturing a mask includes designing a second mask data pattern for forming a first mask data pattern, creating a first emulation pattern, which is determined from the second mask data pattern, using a first emulation, creating a second emulation pattern, which is determined from the first emulation pattern, using a second emulation, comparing a pattern, in which the first and second emulation patterns overlap, with the first mask data pattern, and manufacturing a mask layer, which corresponds to the second mask data pattern, according to results of the comparison.
摘要翻译：制造掩模的方法包括设计用于形成第一掩模数据图案的第二掩模数据图案，使用第一仿真创建从第二掩模数据图案确定的第一仿真图案，创建第二仿真图案，其是第二仿真模式根据第一仿真模式确定，使用第二仿真，将第一和第二仿真模式重叠的模式与第一掩模数据模式进行比较，并根据第二掩模数据模式制造对应于第二掩模数据模式的掩模层比较结果。

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