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21. 发明授权

US08394698B2 NAND flash memory array with cut-off gate line and methods for operating and fabricating the same 有权
标题翻译：具有截止栅极线的NAND闪存阵列及其操作和制造方法
公开(公告)号：US08394698B2
公开(公告)日：2013-03-12
申请号：US13170533
申请日：2011-06-28
申请人： Byung-Gook Park , Seong Jae Cho
发明人： Byung-Gook Park , Seong Jae Cho
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： G11C8/14 , G11C16/0483 , H01L21/26586 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L29/66833
摘要： A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.
摘要翻译：提供NAND闪存阵列，其操作方法及其制造方法。 NAND闪速存储器阵列在控制栅极下方具有截止栅极线，以便利用一个控制栅极（即共享字线）独立地操作具有垂直沟道的两个单元。与传统的垂直通道结构相比，存储单元面积显着减小，并且更好地用于高集成度。共享截止门在编程操作期间关闭，并防止通过自增强效应对相对的单元进行编程。在读取操作期间可以用共享字线（控制门）进行电屏蔽，并且使对置单元的存储条件的影响最小化。而且，NAND闪存阵列可以通过使用传统的CMOS工艺来制造。

22. 发明申请

US20090207667A1 NAND FLASH MEMORY ARRAY WITH CUT-OFF GATE LINE AND METHODS FOR OPERATING AND FABRICATING THE SAME 有权
标题翻译：具有切断栅极线的NAND闪存阵列及其操作和制造方法
公开(公告)号：US20090207667A1
公开(公告)日：2009-08-20
申请号：US12361107
申请日：2009-01-28
申请人： Byung-Gook Park , Seongjae Cho
发明人： Byung-Gook Park , Seongjae Cho
IPC分类号： G11C16/16 , H01L29/792 , H01L21/336 , G11C16/06 , G11C5/14
CPC分类号： G11C8/14 , G11C16/0483 , H01L21/26586 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L29/66833
摘要： A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.
摘要翻译：提供NAND闪存阵列，其操作方法及其制造方法。 NAND闪速存储器阵列在控制栅极下方具有截止栅极线，以便利用一个控制栅极（即共享字线）独立地操作具有垂直沟道的两个单元。与传统的垂直通道结构相比，存储单元面积显着减小，并且更好地用于高集成度。共享截止门在编程操作期间关闭，并防止通过自增强效应对相对的单元进行编程。在读取操作期间可以用共享字线（控制门）进行电屏蔽，并且使对置单元的存储条件的影响最小化。而且，NAND闪存阵列可以通过使用传统的CMOS工艺来制造。

23. 发明申请

US20080128757A1 Non-volatile memory devices including vertical channels, methods of operating, and methods of fabricating the same 有权
标题翻译：包括垂直通道的非易失性存储器件，操作方法及其制造方法
公开(公告)号：US20080128757A1
公开(公告)日：2008-06-05
申请号：US11999135
申请日：2007-12-04
申请人： Soo-Doo Chae , Chung-Woo Kim , Chan-Jin Park , Jeong-Hee Han , Byung-Gook Park , Il-Han Park
发明人： Soo-Doo Chae , Chung-Woo Kim , Chan-Jin Park , Jeong-Hee Han , Byung-Gook Park , Il-Han Park
IPC分类号： G11C11/407 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0416 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A flash memory device can include a semiconductor pin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor pin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor pin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.
摘要翻译：闪速存储器件可以包括从第一导电类型的半导体衬底突出以在一个方向上延伸的半导体引脚，分别设置到半导体引脚的上部和下部的第一掺杂层和第二掺杂层，彼此垂直间隔开，第一和第二掺杂层具有第二导电类型，并且多个字线在半导体引脚的顶部和侧壁上延伸以与该方向相交。字线与第一掺杂层和第二掺杂层重叠以具有垂直沟道。

24. 发明申请

US20070069310A1 Semiconductor controlled rectifiers for electrostatic discharge protection 审中-公开
标题翻译：半导体控制整流器用于静电放电保护
公开(公告)号：US20070069310A1
公开(公告)日：2007-03-29
申请号：US11525021
申请日：2006-09-22
申请人： Ki-Whan Song , Jong-Duk Lee , Byung-Gook Park
发明人： Ki-Whan Song , Jong-Duk Lee , Byung-Gook Park
IPC分类号： H01L29/76
CPC分类号： H01L29/7436 , H01L27/0262
摘要： A silicon controlled rectifier (SCR) may include a first well and a second well formed within a substrate. A first junction region and a second junction region may be formed within the first well. A third junction region may include a first portion formed within the first well and a second portion formed within the substrate. A fourth junction region may include a first portion formed within the second well and a second portion formed within the substrate. A gate electrode may be formed on the substrate between the third junction region and the fourth junction region. A fifth junction region may be formed within a region of the substrate.
摘要翻译：可控硅整流器（SCR）可以包括在衬底内形成的第一阱和第二阱。第一接合区域和第二接合区域可以形成在第一阱内。第三结区域可以包括形成在第一阱内的第一部分和形成在衬底内的第二部分。第四结区域可以包括形成在第二阱内的第一部分和形成在衬底内的第二部分。可以在第三接合区域和第四接合区域之间的衬底上形成栅电极。第五结区域可以形成在衬底的区域内。

25. 发明申请

US20150303202A1 SEMICONDUCTOR DEVICES HAVING VERTICAL DEVICE AND NON-VERTICAL DEVICE AND METHODS OF FORMING THE SAME 有权
标题翻译：具有垂直装置和非垂直装置的半导体装置及其形成方法
公开(公告)号：US20150303202A1
公开(公告)日：2015-10-22
申请号：US14789433
申请日：2015-07-01
申请人： Min-Chul Sun , Byung-Gook Park
发明人： Min-Chul Sun , Byung-Gook Park
IPC分类号： H01L27/11 , H01L29/78
CPC分类号： H01L27/1104 , H01L21/823487 , H01L21/823885 , H01L27/092 , H01L29/7827
摘要： A semiconductor device comprises a substrate extending in a horizontal direction and a vertical transistor on the substrate. The vertical transistor comprises: a first diffusion region on the substrate; a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate.
摘要翻译：半导体器件包括在水平方向上延伸的衬底和在衬底上的垂直晶体管。所述垂直晶体管包括：所述基板上的第一扩散区域; 在所述第一扩散区域上的相对于所述基板的延伸部的水平方向在垂直方向上延伸的沟道区域; 沟道区上的第二扩散区; 以及在沟道区的侧壁处和绝缘的栅电极。水平晶体管位于衬底上，水平晶体管包括：在衬底上的第一扩散区和第二扩散区，彼此间隔开; 在所述第一扩散区域和所述第二扩散区域之间的衬底上的沟道区域; 以及沟道区上的栅极，并与沟道区分离。垂直晶体管的栅电极的一部分和水平晶体管的栅电极的一部分在垂直方向上相对于衬底处于相同的垂直位置。

26. 发明申请

US20140291616A1 COMPOUND TUNNELING FIELD EFFECT TRANSISTOR INTEGRATED ON SILICON SUBSTRATE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：集成在硅基板上的复合隧道场效应晶体管及其制造方法
公开(公告)号：US20140291616A1
公开(公告)日：2014-10-02
申请号：US14357685
申请日：2011-12-30
申请人： Byung-Gook Park , Seongjae Cho , In Man Kang
发明人： Byung-Gook Park , Seongjae Cho , In Man Kang
IPC分类号： H01L29/775 , H01L29/66
CPC分类号： H01L29/775 , H01L29/0657 , H01L29/267 , H01L29/42312 , H01L29/66356 , H01L29/66439 , H01L29/7391
摘要： Compound tunneling field effect transistors integrated on a silicon substrate are provided with increased tunneling efficiency and an abrupt band slope by forming a source region with a material having a bandgap at least 0.4 electron volts (eV) narrower than that of silicon to increase a driving current (ON current) by forming a channel region with a material having almost no difference in lattice constant from a source region and having a high electron mobility at least 5 times higher than silicon. ON/OFF current ratio simultaneously is increased by forming a drain region with a material having a bandgap at least as wide as a channel region material to restrain OFF current. Tunneling field effect transistors having various threshold voltages according to circuit designs are formed easily by adding a specific material with an electron affinity less than a source region material when forming a channel region.
摘要翻译：集成在硅衬底上的复合隧道场效应晶体管具有增加的隧穿效率和突变带斜率，通过形成具有比硅的带隙更小的至少0.4电子伏（eV）的带隙的材料的源极区，以增加驱动电流（导通电流）通过形成具有与源极区域的晶格常数几乎没有差异的材料的沟道区域，并且具有比硅高至少5倍的高电子迁移率。通过用具有至少与沟道区域材料一样宽的带隙的材料形成漏极区域来同时增加ON / OFF电流比，以限制关断电流。通过在形成沟道区域时，通过添加小于源区材料的电子亲和力的特定材料，容易地形成具有根据电路设计的各种阈值电压的隧穿场效应晶体管。

27. 发明授权

US08786004B2 3D stacked array having cut-off gate line and fabrication method thereof 有权
标题翻译：具有截止栅极线的3D堆叠阵列及其制造方法
公开(公告)号：US08786004B2
公开(公告)日：2014-07-22
申请号：US13023646
申请日：2011-02-09
申请人： Byung-Gook Park , Seongjae Cho , Won Bo Shim
发明人： Byung-Gook Park , Seongjae Cho , Won Bo Shim
IPC分类号： H01L29/792
CPC分类号： H01L27/11565 , H01L27/11578
摘要： A three-dimensional stacked flash memory array having cut-off gate line and a fabricating method of the same are provided. The flash memory array enables to operate two memory cells by each word line, to produce a high integrity without limitation by vertical stacks of word lines, to increase operating speed and uniformity of electrical property between cells by using a single crystal substrate as a channel region, and to reduce a fabricating cost to a great amount by a fabricating method which is including steps of forming a plurality of trenches in a semiconductor substrate and stacking repeatedly a conductive material interlaid with an insulating layer from bottom of each trench to form a cut-off gate line and a plurality of word lines.
摘要翻译：提供具有截止栅极线的三维堆叠式闪存阵列及其制造方法。闪存阵列使得能够通过每个字线操作两个存储器单元，以产生高完整性而不受字线的垂直堆叠的限制，以通过使用单晶衬底作为沟道区域来增加单元之间的电性能的操作速度和均匀性并且通过包括在半导体衬底中形成多个沟槽并在每个沟槽的底部重叠层叠有绝缘层的导电材料的步骤的制造方法来大大减少制造成本，关门线和多条字线。

28. 发明申请

US20130140612A1 FIELD-EFFECT TRANSISTOR HAVING BACK GATE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有后盖的场效应晶体管及其制造方法
公开(公告)号：US20130140612A1
公开(公告)日：2013-06-06
申请号：US13554066
申请日：2012-07-20
申请人： Min-Chul Sun , Byung-Gook Park
发明人： Min-Chul Sun , Byung-Gook Park
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/0673 , H01L29/7854 , H01L29/78648 , H01L29/78696
摘要： A back-bias region is disposed on a substrate. A buried insulating layer covers the substrate and the back-bias region. A body is formed on the buried insulating layer and partially overlaps the back-bias region. A drain is in contact with the body. A gate electrode covers top and lateral surfaces of the body.
摘要翻译：背面偏置区域设置在基板上。掩埋绝缘层覆盖基板和背偏置区域。在掩埋绝缘层上形成一体并且部分地与背偏置区重叠。排水管与身体接触。栅电极覆盖身体的顶表面和侧表面。

29. 发明申请

US20110256680A1 NAND FLASH MEMORY ARRAY WITH CUT-OFF GATE LINE AND METHODS FOR OPERATING AND FABRICATING THE SAME 有权
标题翻译：具有切断栅极线的NAND闪存阵列及其操作和制造方法
公开(公告)号：US20110256680A1
公开(公告)日：2011-10-20
申请号：US13170533
申请日：2011-06-28
申请人： Byung-Gook Park , Seongjae Cho
发明人： Byung-Gook Park , Seongjae Cho
IPC分类号： H01L21/8247
CPC分类号： G11C8/14 , G11C16/0483 , H01L21/26586 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L29/66833
摘要： A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.
摘要翻译：提供NAND闪存阵列，其操作方法及其制造方法。 NAND闪速存储器阵列在控制栅极下方具有截止栅极线，以便利用一个控制栅极（即共享字线）独立地操作具有垂直沟道的两个单元。与传统的垂直通道结构相比，存储单元面积显着减小，并且更好地用于高集成度。共享截止门在编程操作期间关闭，并防止通过自增强效应对相对的单元进行编程。在读取操作期间可以用共享字线（控制门）进行电屏蔽，并且使对置单元的存储条件的影响最小化。而且，NAND闪存阵列可以通过使用传统的CMOS工艺来制造。

30. 发明授权

US07928501B2 Semiconductor device and methods of forming and operating the same 有权
标题翻译：半导体器件及其形成和操作的方法
公开(公告)号：US07928501B2
公开(公告)日：2011-04-19
申请号：US12458218
申请日：2009-07-06
申请人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
发明人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.
摘要翻译：提供半导体器件以及形成和操作半导体器件的方法。半导体器件可以包括从半导体衬底延伸并且二维地设置在半导体衬底上的有源柱，在一个方向上连接有源柱的上部互连，与上部互连交叉的下部互连，并且设置在有源柱之间，跨越上部的字线互连并且布置在活动柱之间，以及布置在字线和活动柱之间的数据存储图案。

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