专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07812397B2 Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof 有权
标题翻译：在UTC和源极/漏极区域下方形成具有不同深度和不同厚度的BOX区域上的超薄沟道（UTC）MOSFET结构及其制造方法
公开(公告)号：US07812397B2
公开(公告)日：2010-10-12
申请号：US12166285
申请日：2008-07-01
申请人： Changguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
发明人： Changguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/3003 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78603 , H01L29/78621 , H01L29/78696
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 UT SOI沟道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 BOX1区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的BOX2区域的上部与栅极自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二深度

22. 发明授权

US06703274B1 Buried strap with limited outdiffusion and vertical transistor DRAM 有权
标题翻译：带有限制扩散和垂直晶体管DRAM的埋地带
公开(公告)号：US06703274B1
公开(公告)日：2004-03-09
申请号：US10336988
申请日：2003-01-03
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Raymond Van Roijen
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Raymond Van Roijen
IPC分类号： H02L218242
CPC分类号： H01L27/10867 , H01L27/10864 , H01L27/10876
摘要： A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.
摘要翻译：具有垂直晶体管的DRAM单元通过在初始掩埋带扩散之前移动影响热预算的高温步骤而形成具有减小的横向扩展的埋地带外扩散。栅极导体形成为两个阶段，其中多个侧壁被放置在牺牲沟槽顶部氧化物之上，以在形成LDD延伸之前形成自对准多晶硅绝缘体结构。

23. 发明授权

US07436029B2 High performance CMOS device structures and method of manufacture 有权
标题翻译：高性能CMOS器件结构及其制造方法
公开(公告)号：US07436029B2
公开(公告)日：2008-10-14
申请号：US11867271
申请日：2007-10-04
申请人： Bruce B. Doris , Dureseti Chidambarrao , Suk Hoon Ku
发明人： Bruce B. Doris , Dureseti Chidambarrao , Suk Hoon Ku
IPC分类号： H01L29/76
CPC分类号： H01L29/7842 , H01L21/823864 , H01L29/7843 , Y10S257/90 , Y10S438/938
摘要： A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.
摘要翻译：半导体器件结构包括形成在同一衬底上的至少两个场效应晶体管，第一场效应晶体管包括具有第一宽度的间隔物，第二场效应晶体管包括具有第二宽度的压缩间隔物，第一宽度不同于所述第一宽度第二宽度。优选地，第一宽度比第二宽度窄。拉伸应力介电膜在晶体管上形成阻挡蚀刻停止层。

24. 发明授权

US06734056B2 Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell 失效
标题翻译： 6F2旋转混合DRAM单元的自对准穿通停止
公开(公告)号：US06734056B2
公开(公告)日：2004-05-11
申请号：US10341831
申请日：2003-01-14
申请人： Jack A. Mandelman , Dureseti Chidambarrao
发明人： Jack A. Mandelman , Dureseti Chidambarrao
IPC分类号： H01L218238
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate conductor regions and two gates formed on opposing sidewalls of the MOSFETs. The memory cell structure also includes a plurality of wordlines overlaying the double-gated vertical MOSFETs and in contact with the exposed gate conductor regions, and a plurality of bitlines that are orthogonal to the wordlines. Trench isolation regions are located adjacent to the rows of memory cells. The memory cell structure also includes a plurality of punch through stop regions located in the Si-containing substrate and self-aligned to the wordlines and bitlines. A portion of the punch through stop regions overlap each other under the bitlines and each region serves to electrically isolate adjacent buried-strap regions from each other.
摘要翻译： 6F 2存储单元结构及其制造方法。存储单元结构包括位于含Si衬底中的以行和列排列的多个存储单元。每个存储单元包括具有暴露的栅极导体区域和形成在MOSFET的相对侧壁上的两个栅极的双门控垂直MOSFET。存储单元结构还包括覆盖双门控垂直MOSFET并与暴露的栅极导体区域接触的多个字线以及与字线正交的多个位线。沟槽隔离区位于与存储单元行相邻的位置。存储单元结构还包括位于含硅衬底中并与字线和位线自对准的多个穿通停止区域。穿通停止区域的一部分在位线之下彼此重叠，并且每个区域用于将相邻的掩埋区域彼此电隔离。

25. 发明授权

US06707095B1 Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation 有权
标题翻译：用于改进垂直MOSFET DRAM单元到单元隔离的结构和方法
公开(公告)号：US06707095B1
公开(公告)日：2004-03-16
申请号：US10290400
申请日：2002-11-06
申请人： Dureseti Chidambarrao , Jack A. Mandelman , Carl J. Radens
发明人： Dureseti Chidambarrao , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10867
摘要： A method is provided for forming a vertical transistor memory cell structure with back-to-back FET cells which are formed in a planar semiconductor substrate with a plurality of deep trenches having vertical FET devices and a plurality of capacitors each located in a separate trench that is formed in the semiconductor substrate. Bilateral outdiffusion strap regions are formed extending into a doped semiconductor well region in the substrate. There are confronting pairs of outdiffusion strap regions extending from adjacent deep benches into the doped well region. An isolation diffusion region is formed in the doped well separating the confronting isolation diffusion regions by extending therebetween.
摘要翻译：提供了一种用于形成具有背对背FET单元的垂直晶体管存储单元结构的方法，其形成在具有多个具有垂直FET器件的深沟槽的平面半导体衬底中，并且多个电容器分别位于单独的沟槽中，形成在半导体衬底中。形成延伸到衬底中的掺杂半导体阱区域中的双边扩散带区域。存在从相邻的深长板延伸到掺杂阱区域的面向对的向外扩散带区域。在掺杂阱中形成隔离扩散区，通过在相互隔离扩散区之间延伸来分离相对的隔离扩散区。

26. 发明授权

US06573561B1 Vertical MOSFET with asymmetrically graded channel doping 失效
标题翻译：具有不对称梯度通道掺杂的垂直MOSFET
公开(公告)号：US06573561B1
公开(公告)日：2003-06-03
申请号：US10096192
申请日：2002-03-11
申请人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Kevin McStay
发明人： Dureseti Chidambarrao , Ramachandra Divakaruni , Jack A. Mandelman , Kevin McStay
IPC分类号： H01L2976
CPC分类号： H01L27/10864 , H01L27/10876 , H01L29/1041 , H01L29/7827
摘要： Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.
摘要翻译：垂直MOSFET晶体管中的短沟道效应显着降低，在具有垂直非对称阈值注入的晶体管中，DRAM单元中的结漏电减少，其它器件参数不受影响。优选实施例具有将阈值注入的峰值从源极和漏极之间的中途的常规位置移动到不超过源极底部的沟道长度的三分之一的点。

27. 发明授权

US06222244B1 Electrically blowable fuse with reduced cross-sectional area 失效
标题翻译：具有减小横截面积的可电熔保险丝
公开(公告)号：US06222244B1
公开(公告)日：2001-04-24
申请号：US09093903
申请日：1998-06-08
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译：半导体保险丝位于用于连接布线的导体之间。保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

28. 发明授权

US5729052A Integrated ULSI heatsink 失效
标题翻译：集成ULSI散热器
公开(公告)号：US5729052A
公开(公告)日：1998-03-17
申请号：US667210
申请日：1996-06-20
申请人： William R. Tonti , Jack A. Mandelman , Jerzy M. Zalesinski , Toshiharu Furukawa , Son V. Nguyen , Dureseti Chidambarrao
发明人： William R. Tonti , Jack A. Mandelman , Jerzy M. Zalesinski , Toshiharu Furukawa , Son V. Nguyen , Dureseti Chidambarrao
IPC分类号： H01L21/60 , H01L23/367 , H01L29/06 , H01L29/34 , H01L23/34
CPC分类号： H01L24/27 , H01L23/367 , H01L24/32 , H01L24/83 , H01L29/0657 , H01L29/34 , H01L2224/03505 , H01L2224/04026 , H01L2224/16225 , H01L2224/16227 , H01L2224/32057 , H01L2224/32059 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/8319 , H01L2224/83385 , H01L2224/83801 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10158 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/181 , Y10S438/928 , Y10S438/964
摘要： A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) followed by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips. The heatsink itself is prepared by first optionally roughening the surface and metalizing the backside of the heatsink with metal interlayer. Next, the chip is thermally attached to the heatsink by reflowing the thermally conductive reflowable material.
摘要翻译：简单且低成本的ULSI集成散热器通过将散热材料集成到硅晶片中更有效地从硅封装中去除热量，将现有的二维技术转化为三维。高功率集成ULSI封装和散热器的制造开始于制造集成电路晶片，直到将晶片切割成单个芯片。晶片的正面受到保护，而晶片的背面露出。暴露的背面通过化学和/或机械过程粗糙化。任选地，然后执行吸气过程以除去杂质。然后将粗糙的背面涂覆有金属中间层，优选铝（Al），随后涂覆铬（Cr）。一层铜（Cu）任选地涂覆在金属夹层上。高度导电的可回流材料，例如焊料或金共晶，沉积在金属夹层上。此时，晶片被切割成芯片。散热器本身通过首先任选地使表面粗糙化并用金属中间层金属化散热器的背面来制备。接下来，通过回流导热的可回流材料将芯片热连接到散热器。

29. 发明授权

US07737014B2 Reduction of boron diffusivity in pFETs 失效
标题翻译：降低pFET中的硼扩散率
公开(公告)号：US07737014B2
公开(公告)日：2010-06-15
申请号：US10596249
申请日：2003-12-08
申请人： Frederick William Buehrer , Dureseti Chidambarrao , Bruce B. Doris , Hsiang-Jen Huang , Haining Yang
发明人： Frederick William Buehrer , Dureseti Chidambarrao , Bruce B. Doris , Hsiang-Jen Huang , Haining Yang
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/7842 , H01L21/22 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.
摘要翻译：应用于由半导体材料的结构或主体（例如衬底或层）限定的边界处的应力膜提供了靠近边界的半导体材料中的拉应力和压缩应力的变化，并用于在退火过程中修饰硼扩散速率，从而改变最终的硼浓度。在场效应晶体管的情况下，栅极结构可以形成有或不具有侧壁以调节边界相对于源极/漏极，延伸和/或晕轮植入物的位置。可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。可以通过相同的工艺步骤同时实现nFET和pFET的结电容的减小。

30. 发明授权

US07312134B2 Dual stressed SOI substrates 有权
标题翻译：双重应力SOI衬底
公开(公告)号：US07312134B2
公开(公告)日：2007-12-25
申请号：US11741441
申请日：2007-04-27
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Huilong Zhu
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Huilong Zhu
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式