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21. 发明授权

US07657767B2 Cache leakage shut-off mechanism 有权
标题翻译：缓存泄漏关闭机制
公开(公告)号：US07657767B2
公开(公告)日：2010-02-02
申请号：US11174204
申请日：2005-06-30
申请人： Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
发明人： Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/32 , G06F1/3287 , G11C11/417 , Y02D10/171
摘要： In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.
摘要翻译：在本发明的一个实施例中，提供了一种用于控制高速缓存子阵列的泄漏的技术。本文公开了其它实施例。睡眠和关闭电路连接在虚拟供应终端和第一物理供应终端之间，以便在关闭模式下禁用高速缓存子阵列时减少从高速缓存子阵列的泄漏。高速缓存子阵列连接在虚拟供电终端和第二物理供应终端之间。有源电路并联连接到睡眠和关闭电路，以使高速缓存子阵列处于正常模式，并在关闭模式下禁用高速缓存子阵列。

22. 发明申请

US20060067134A1 Dynamic multi-Vcc scheme for SRAM cell stability control 有权
标题翻译：用于SRAM单元稳定性控制的动态多Vcc方案
公开(公告)号：US20060067134A1
公开(公告)日：2006-03-30
申请号：US10950740
申请日：2004-09-27
申请人： Kevin Zhang , Fatih Hamzaoglu , Lin Ma
发明人： Kevin Zhang , Fatih Hamzaoglu , Lin Ma
IPC分类号： G11C7/10
CPC分类号： G11C5/14 , G11C11/413
摘要： A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.
摘要翻译：动态多电压存储器阵列具有不同偏置条件的SRAM单元，具体取决于单元的工作模式。所选择的SRAM单元在执行读取操作时接收第一电压，并且当执行写入操作时接收第二电压。通过针对两个不同的操作偏置单元格，可以实现读取和写入操作的完全解耦。所公开的存储器阵列以及结合多电压能力的未来SRAM设计因此避免了读写操作的冲突要求。由于读取稳定性和写入裕度的提高，存储器阵列的随机单位故障降低。

23. 发明授权

US08456946B2 NAND logic word line selection 有权
标题翻译： NAND逻辑字线选择
公开(公告)号：US08456946B2
公开(公告)日：2013-06-04
申请号：US12928949
申请日：2010-12-22
申请人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
发明人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
IPC分类号： G11C8/00
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/10 , G11C11/4087
摘要： A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
摘要翻译：公开了一种用于在DRAM中选择字线驱动器的NAND架构。低，中，高范围的分离地址用于选择最终的字线驱动。字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

24. 发明授权

US06879531B2 Reduced read delay for single-ended sensing 失效
标题翻译：降低单端感测的读延迟
公开(公告)号：US06879531B2
公开(公告)日：2005-04-12
申请号：US10324177
申请日：2002-12-19
申请人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
IPC分类号： G11C7/12 , G11C7/22 , G11C8/08 , G11C7/00 , G11C11/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/22 , G11C8/08 , G11C2207/2281
摘要： An offset line to substantially cancel the capacitive coupling effects of a select line to a memory cell. When the select line transitions to cause a stored memory state in the memory cell to be placed onto a sense line, capacitive coupling from the select line to the sense line is substantially cancelled by capacitive coupling, of an opposite polarity, from an offset line to the sense line. Without the opposing effects of the offset line, the capacitive coupling from the select line would raise the pre-charge voltage level on the sense line, which would then require a longer time to discharge down to the input threshold of a sense gate that detects the stored state that was in the memory cell.
摘要翻译：偏移线，用于基本上消除选择线对存储器单元的电容耦合效应。当选择线转变以使得存储器单元中存储的存储器状态被放置在感测线上时，从选择线到感测线的电容耦合基本上被相反极性的电容耦合从偏移线到感觉线。没有偏移线的相反的影响，来自选择线的电容耦合将提高感测线上的预充电电压电平，这将需要更长的时间来放电到感测门的输入阈值，该感测门检测存储在存储单元中的状态。

25. 发明授权

US06519176B1 Dual threshold SRAM cell for single-ended sensing 失效
标题翻译：用于单端感测的双阈值SRAM单元
公开(公告)号：US06519176B1
公开(公告)日：2003-02-11
申请号：US09675579
申请日：2000-09-29
申请人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.
摘要翻译：描述了用于单端感测的六晶体管SRAM单元以及相关的存储器架构。该单元包括通过一对通道晶体管连接到互补位线的双稳态电路。一个通道晶体管具有比另一个晶体管更低的阈值电压。较低的阈值电压用于通过其中一条位线将单元耦合到单端读出放大器。在一个实施例中，少于阵列中的所有位线被预充电以便减少阵列中的功耗。

26. 发明授权

US08547777B2 Nor logic word line selection 有权
标题翻译：也不是逻辑字线选择
公开(公告)号：US08547777B2
公开(公告)日：2013-10-01
申请号：US12928989
申请日：2010-12-22
申请人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
发明人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
IPC分类号： G11C8/08 , G11C8/10 , G11C8/02
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/10 , G11C16/08
摘要： A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
摘要翻译：公开了一种用于在DRAM中选择字线驱动器的NOR架构。用于选择最终字线驱动程序的低，中，高范围内单独解码的地址的完成。字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

27. 发明申请

US20120163114A1 NAND logic word line selection 有权
标题翻译： NAND逻辑字线选择
公开(公告)号：US20120163114A1
公开(公告)日：2012-06-28
申请号：US12928949
申请日：2010-12-22
申请人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
发明人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
IPC分类号： G11C8/08
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/10 , G11C11/4087
摘要： A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
摘要翻译：公开了一种用于在DRAM中选择字线驱动器的NAND架构。低，中，高范围的分离地址用于选择最终的字线驱动。字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正。

28. 发明授权

US06351156B1 Noise reduction circuit 有权
标题翻译：降噪电路
公开(公告)号：US06351156B1
公开(公告)日：2002-02-26
申请号：US09740104
申请日：2000-12-18
申请人： Fatih Hamzaoglu , Yibin Ye , Dinesh Somasekhar , Vivek K. De
发明人： Fatih Hamzaoglu , Yibin Ye , Dinesh Somasekhar , Vivek K. De
IPC分类号： H03F345
CPC分类号： G11C7/02 , G11C7/1048 , G11C7/1051 , G11C7/1057 , G11C7/1069
摘要： A circuit and method for reducing noise in a memory circuit is disclosed. In one embodiment, the circuit includes an amplifier, a first transistor and a second transistor. The first transistor is capable of pulling up a first input port of the amplifier in response to a complement of the second memory signal. The second transistor is capable of pulling of a second input port of the amplifier in response to a complement of the first memory signal. In one embodiment, the method includes receiving a first memory signal at a first input port of an amplifier, receiving a second memory signal at a second input port of the amplifier, and pulling up the second input port in response to a complement of the first memory signal.
摘要翻译：公开了一种用于降低存储器电路中的噪声的电路和方法。在一个实施例中，电路包括放大器，第一晶体管和第二晶体管。第一晶体管能够响应于第二存储器信号的补码而提升放大器的第一输入端口。第二晶体管能够响应于第一存储器信号的补码而拉动放大器的第二输入端口。在一个实施例中，该方法包括在放大器的第一输入端口处接收第一存储器信号，在放大器的第二输入端口接收第二存储器信号，以及响应于第一输入端口记忆信号

29. 发明申请

US20120163115A1 Nor logic word line selection 有权
标题翻译：也不是逻辑字线选择
公开(公告)号：US20120163115A1
公开(公告)日：2012-06-28
申请号：US12928989
申请日：2010-12-22
申请人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
发明人： Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
IPC分类号： G11C8/08
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/10 , G11C16/08
摘要： A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
摘要翻译：公开了一种用于在DRAM中选择字线驱动器的NOR架构。用于选择最终字线驱动程序的低，中，高范围内单独解码的地址的完成。字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

30. 发明授权

US06801465B2 Apparatus and method for a memory storage cell leakage cancellation scheme 有权
标题翻译：用于存储器存储单元泄漏消除方案的装置和方法
公开(公告)号：US06801465B2
公开(公告)日：2004-10-05
申请号：US10461293
申请日：2003-06-13
申请人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.
摘要翻译：描述了具有耦合在第一位线和第二位线之间的多个存储单元的装置。该装置还具有第一晶体管，其对第一位线进行预充电，并为多个存储单元中的任何一个提供从第一位线提取的一个或多个泄漏电流的第一电流。该装置还具有第二晶体管，其对第二位线进行预充电并且为多个存储单元中的任一个提供从第二位线提取的一个或多个泄漏电流的第二电流供应。

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