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1. 发明授权

US07403426B2 Memory with dynamically adjustable supply 有权
标题翻译：内存动态可调电源
公开(公告)号：US07403426B2
公开(公告)日：2008-07-22
申请号：US11137905
申请日：2005-05-25
申请人： Fatih Hamzaoglu , Kevin Zhang , Nam Sung Kim , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , Bo Zheng
发明人： Fatih Hamzaoglu , Kevin Zhang , Nam Sung Kim , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , Bo Zheng
IPC分类号： G11C11/34
CPC分类号： G11C5/14 , G11C11/413
摘要： In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
摘要翻译：在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。可以公开和/或要求保护其他实施例。

2. 发明授权

US06879531B2 Reduced read delay for single-ended sensing 失效
标题翻译：降低单端感测的读延迟
公开(公告)号：US06879531B2
公开(公告)日：2005-04-12
申请号：US10324177
申请日：2002-12-19
申请人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
IPC分类号： G11C7/12 , G11C7/22 , G11C8/08 , G11C7/00 , G11C11/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/22 , G11C8/08 , G11C2207/2281
摘要： An offset line to substantially cancel the capacitive coupling effects of a select line to a memory cell. When the select line transitions to cause a stored memory state in the memory cell to be placed onto a sense line, capacitive coupling from the select line to the sense line is substantially cancelled by capacitive coupling, of an opposite polarity, from an offset line to the sense line. Without the opposing effects of the offset line, the capacitive coupling from the select line would raise the pre-charge voltage level on the sense line, which would then require a longer time to discharge down to the input threshold of a sense gate that detects the stored state that was in the memory cell.
摘要翻译：偏移线，用于基本上消除选择线对存储器单元的电容耦合效应。当选择线转变以使得存储器单元中存储的存储器状态被放置在感测线上时，从选择线到感测线的电容耦合基本上被相反极性的电容耦合从偏移线到感觉线。没有偏移线的相反的影响，来自选择线的电容耦合将提高感测线上的预充电电压电平，这将需要更长的时间来放电到感测门的输入阈值，该感测门检测存储在存储单元中的状态。

3. 发明授权

US06351156B1 Noise reduction circuit 有权
标题翻译：降噪电路
公开(公告)号：US06351156B1
公开(公告)日：2002-02-26
申请号：US09740104
申请日：2000-12-18
申请人： Fatih Hamzaoglu , Yibin Ye , Dinesh Somasekhar , Vivek K. De
发明人： Fatih Hamzaoglu , Yibin Ye , Dinesh Somasekhar , Vivek K. De
IPC分类号： H03F345
CPC分类号： G11C7/02 , G11C7/1048 , G11C7/1051 , G11C7/1057 , G11C7/1069
摘要： A circuit and method for reducing noise in a memory circuit is disclosed. In one embodiment, the circuit includes an amplifier, a first transistor and a second transistor. The first transistor is capable of pulling up a first input port of the amplifier in response to a complement of the second memory signal. The second transistor is capable of pulling of a second input port of the amplifier in response to a complement of the first memory signal. In one embodiment, the method includes receiving a first memory signal at a first input port of an amplifier, receiving a second memory signal at a second input port of the amplifier, and pulling up the second input port in response to a complement of the first memory signal.
摘要翻译：公开了一种用于降低存储器电路中的噪声的电路和方法。在一个实施例中，电路包括放大器，第一晶体管和第二晶体管。第一晶体管能够响应于第二存储器信号的补码而提升放大器的第一输入端口。第二晶体管能够响应于第一存储器信号的补码而拉动放大器的第二输入端口。在一个实施例中，该方法包括在放大器的第一输入端口处接收第一存储器信号，在放大器的第二输入端口接收第二存储器信号，以及响应于第一输入端口记忆信号

4. 发明授权

US06801465B2 Apparatus and method for a memory storage cell leakage cancellation scheme 有权
标题翻译：用于存储器存储单元泄漏消除方案的装置和方法
公开(公告)号：US06801465B2
公开(公告)日：2004-10-05
申请号：US10461293
申请日：2003-06-13
申请人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.
摘要翻译：描述了具有耦合在第一位线和第二位线之间的多个存储单元的装置。该装置还具有第一晶体管，其对第一位线进行预充电，并为多个存储单元中的任何一个提供从第一位线提取的一个或多个泄漏电流的第一电流。该装置还具有第二晶体管，其对第二位线进行预充电并且为多个存储单元中的任一个提供从第二位线提取的一个或多个泄漏电流的第二电流供应。

5. 发明授权

US06608786B2 Apparatus and method for a memory storage cell leakage cancellation scheme 有权
公开(公告)号：US06608786B2
公开(公告)日：2003-08-19
申请号：US09823575
申请日：2001-03-30
申请人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.

6. 发明申请

US20060268626A1 Memory with dynamically adjustable supply 有权
标题翻译：内存动态可调电源
公开(公告)号：US20060268626A1
公开(公告)日：2006-11-30
申请号：US11137905
申请日：2005-05-25
申请人： Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
发明人： Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
IPC分类号： G11C7/10
CPC分类号： G11C5/14 , G11C11/413
摘要： In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
摘要翻译：在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。可以公开和/或要求保护其他实施例。

7. 发明授权

US07385865B2 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US07385865B2
公开(公告)日：2008-06-10
申请号：US11001870
申请日：2004-12-01
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Gunjan H. Pandya , Vivek K. De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Gunjan H. Pandya , Vivek K. De
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C11/419
摘要： In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
摘要翻译：在一个实施例中，提供了包括一个或多个列的存储器阵列，每个列包括被分成位单元组的多个位单元，每组比特单元可控制地耦合到单独的位线。

8. 发明授权

US07355246B2 Memory cell without halo implant 有权
标题翻译：无光晕植入的记忆细胞
公开(公告)号：US07355246B2
公开(公告)日：2008-04-08
申请号：US11268430
申请日：2005-11-07
申请人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L29/76
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/0214 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
摘要翻译：一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷第二种载体。根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结是不偏不倚的一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

9. 发明授权

US07321502B2 Non volatile data storage through dielectric breakdown 有权
标题翻译：非易失性数据存储通过介质击穿
公开(公告)号：US07321502B2
公开(公告)日：2008-01-22
申请号：US10956285
申请日：2004-09-30
申请人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Alavi Mohsen , Vivek K. De
发明人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Alavi Mohsen , Vivek K. De
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.
摘要翻译：描述了一种在驱动电流通过电容器的同时在电容器的电介质材料内感应电介质击穿的方法。电流特定于正在写入电容器的数据。该方法还涉及通过解释由电容器电阻确定的电容器的行为来读取数据，其中电容器的电阻是诱导和驱动的结果。

10. 发明授权

US06992339B2 Asymmetric memory cell 有权
公开(公告)号：US06992339B2
公开(公告)日：2006-01-31
申请号：US10750572
申请日：2003-12-31
申请人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L27/10
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7841
摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

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