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21. 发明申请

US20050105507A1 Power savings in serial link transmitters 失效
标题翻译：串行链路发射机节电
公开(公告)号：US20050105507A1
公开(公告)日：2005-05-19
申请号：US10697514
申请日：2003-10-30
申请人： Steven Clements , Carrie Cox , Hayden Cranford
发明人： Steven Clements , Carrie Cox , Hayden Cranford
IPC分类号： H03K17/16 , H03K19/00 , H04L25/02 , H04B1/26
CPC分类号： H04L25/028 , H03K17/163 , H03K17/164
摘要： Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.
摘要翻译：描述了在串行链路发射机中节省功率的方面。这些方面包括提供段的并行布置，每个段包括串行链路发射机的预缓冲器和输出级电路，并且每个段独立地使能实现多个功率电平和多级预加重，同时保持信号中基本恒定的传播延迟串行链路发射机的路径。另外的方面包括在预缓冲器级电路中提供旁路路径，以实现段中的可控空闲状态，并将预缓冲器电路中的尾电流和电阻负载元件作为转换速率控制能力的切片部分。还包括在发射机信号路径中提供具有预加重延迟电路的控制元件，以允许预加重延迟电路的最后延迟位的反转，以实现预加重权重的极性改变。

22. 发明申请

US20080068038A1 Systems and Methods for Controlling of Electro-Migration 有权
公开(公告)号：US20080068038A1
公开(公告)日：2008-03-20
申请号：US11942241
申请日：2007-11-19
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.

23. 发明申请

US20080018378A1 STRUCTURE AND METHOD FOR PROVIDING PRECISION PASSIVE ELEMENTS 失效
标题翻译：提供精密无源元件的结构和方法
公开(公告)号：US20080018378A1
公开(公告)日：2008-01-24
申请号：US11865432
申请日：2007-10-01
申请人： Douglas Coolbaugh , Hayden Cranford , Terence Hook , Anthony Stamper
发明人： Douglas Coolbaugh , Hayden Cranford , Terence Hook , Anthony Stamper
IPC分类号： H03H7/00
CPC分类号： H01L27/0802 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.
摘要翻译：在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个具有高于目标值的值，并且具有低于目标值的值。每个无源电路元件还具有与其串联的保险丝。还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择元素。

24. 发明申请

US20070279117A1 METHOD AND SYSTEM FOR HIGH FREQUENCY CLOCK SIGNAL GATING 审中-公开
标题翻译：高频时钟信号增益的方法与系统
公开(公告)号：US20070279117A1
公开(公告)日：2007-12-06
申请号：US11769408
申请日：2007-06-27
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, providing a clock gating signal with a timing relationship to a clock signal and a differential pair current to a buffer differential pair load element. Switching the differential pair current from the load element to a buffer differential pair responsive to a gating signal pulse, the gating signal pulse correlated to a first clock signal pulse, the buffer differential pair buffers a second clock signal pulse occurring immediately and sequentially after the first clock signal pulse and successive clock signal pulses as a buffer clock signal output, the output comprising a plurality of pulses each having the clock signal amplitude and the clock signal pulse width.
摘要翻译：提供差分时钟信号门控方法和系统，提供具有与时钟信号的时序关系的时钟选通信号和到缓冲器差分对负载元件的差分对电流。响应于门控信号脉冲将差分对电流从负载元件切换到缓冲差分对，门控信号脉冲与第一时钟信号脉冲相关，缓冲差分对缓冲在第一时钟信号脉冲之后立即和顺序发生的第二时钟信号脉冲时钟信号脉冲和连续时钟信号脉冲作为缓冲时钟信号输出，所述输出包括多个脉冲，每个脉冲具有时钟信号幅度和时钟信号脉冲宽度。

25. 发明申请

US20070254613A1 Overshoot reduction in VCO calibration for serial link phase lock loop (PLL) 失效
标题翻译：用于串行链路锁相环（PLL）的VCO校准过程减少
公开(公告)号：US20070254613A1
公开(公告)日：2007-11-01
申请号：US11411662
申请日：2006-04-26
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman
IPC分类号： H04B7/00
CPC分类号： H03L7/18 , H03L7/0891
摘要： A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter nodes and thus centers the frequency of the VCO before stepping from one frequency band to the next.
摘要翻译：用于跟踪VCO校准的电路设计，方法和系统，而不需要如常规实现中的过度设计的分频器。滤波器复位分量被添加到VCO的输入端。在校准机构/过程中添加了一个处理步骤，该校准机构/过程使滤波器节点短路，并因此在从一个频带到下一个频带之前将VCO的频率居中。

26. 发明申请

US20070164768A1 ON-CHIP ELECTROMIGRATION MONITORING SYSTEM 有权
标题翻译：片上电气监测系统
公开(公告)号：US20070164768A1
公开(公告)日：2007-07-19
申请号：US11306985
申请日：2006-01-18
申请人： Louis Hsu , Hayden Cranford , Oleg Gluschenkov , James Mason , Michael Sorna , Chih-Chao Yang
发明人： Louis Hsu , Hayden Cranford , Oleg Gluschenkov , James Mason , Michael Sorna , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/2884 , G01R31/318533
摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.
摘要翻译：提供一种封装的半导体芯片，其包括半导体芯片和封装元件。半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间，将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时被监测元件的电阻超过阈值。

27. 发明申请

US20070103186A1 Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection 有权
标题翻译：自串式串行链路发射机具有用于振幅，预加重和转换速率控制的分段，以及用于振幅精度和高电压保护的电压调节
公开(公告)号：US20070103186A1
公开(公告)日：2007-05-10
申请号：US11263138
申请日：2005-10-27
申请人： Steven Clements , William Cornwell , Carrie Cox , Hayden Cranford , Todd Rasmus
发明人： Steven Clements , William Cornwell , Carrie Cox , Hayden Cranford , Todd Rasmus
IPC分类号： H03K19/003
CPC分类号： H03K17/164 , H03K19/018585 , H04L25/0272 , H04L25/0278 , H04L25/028
摘要： A circuit design method and transmitter that enables flexible control of amplitude, pre- emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control are enabled by manipulation/selection of normal or inverted inputs for the various segments. Also provided is a mechanism for providing/maintaining accurate output across a self-series terminated (SST) transmitter by regulating the supply voltage. Regulation of the supply voltage allows compatibility with conventional serial link receiver termination voltages and protects the transmitter output devices when those voltages are larger than the normal supply for the devices.
摘要翻译：一种电路设计方法和发射机，其利用具有双重上拉的多个单独可控段的并行配置的分段自串行终端（SSST）发射机的设计来灵活地控制幅度，预加重和转换速率，以及下拉晶体管。幅度控制，转换速率控制和预加重控制可以通过操作/选择各个段的正常或反相输入来实现。还提供了一种用于通过调节电源电压来提供/保持跨越自串式端接（SST）发射器的精确输出的机构。电源电压的调节允许与传统的串行链路接收器终端电压兼容，并在这些电压大于设备的正常供电时保护发射机输出设备。

28. 发明申请

US20070096792A1 Transistor switch with integral body connection to prevent latchup 失效
公开(公告)号：US20070096792A1
公开(公告)日：2007-05-03
申请号：US11263008
申请日：2005-10-31
申请人： Hayden Cranford , Stacy Garvin , Todd Rasmus
发明人： Hayden Cranford , Stacy Garvin , Todd Rasmus
IPC分类号： H03K17/00
CPC分类号： H03K17/161 , H03K2217/0018
摘要： A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

29. 发明申请

US20060008042A1 Analog unidirectional serial link architecture 有权
标题翻译：模拟单向串行链路架构
公开(公告)号：US20060008042A1
公开(公告)日：2006-01-12
申请号：US11225600
申请日：2005-09-13
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Paul Owczarski , Martin Schmatz , Joseph Stevens
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Paul Owczarski , Martin Schmatz , Joseph Stevens
IPC分类号： H03D3/24
CPC分类号： H03L7/0995 , H04L7/0004 , H04L7/0337
摘要： The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
摘要翻译：本发明涉及包括逻辑发射机部分和逻辑接收机部分的统一数字架构。提供了一种用于在包括发射机和接收机部分的有线媒体上传输数字数据的统一的串行链路系统和方法，发射机部分和接收机部分之一包括锁相环（PLL）电路。 PLL电路包括压控振荡器，分频器，相频检测器，电荷泵和多极环路滤波器。一个实施例包括具有数字粗略回路和模拟精细回路的双回路PLL。

30. 发明申请

US20050179467A1 Method and circuit for increased noise immunity for clocking signals in high speed digital systems 失效
标题翻译：用于提高高速数字系统中时钟信号抗噪声的方法和电路
公开(公告)号：US20050179467A1
公开(公告)日：2005-08-18
申请号：US10777952
申请日：2004-02-12
申请人： Hayden Cranford , Joseph Stevens
发明人： Hayden Cranford , Joseph Stevens
IPC分类号： H03K19/00 , H03K19/0185
CPC分类号： H03K19/0005 , H03K19/018585
摘要： Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.
摘要翻译：描述了用于在高速数字系统中提高时钟信号的抗噪声性的方面。这些方面包括使用用于多个负载电路的单个缓冲电路来缓冲差分时钟信号，并且配置单个缓冲器电路以适应接收差分时钟信号的负载电路的数量的变化。配置在调整到负载电路数量的变化时，可实现时钟信号输出的恒定带宽和电压电平。

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