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1. 发明申请

US20070103186A1 Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection 有权
标题翻译：自串式串行链路发射机具有用于振幅，预加重和转换速率控制的分段，以及用于振幅精度和高电压保护的电压调节
公开(公告)号：US20070103186A1
公开(公告)日：2007-05-10
申请号：US11263138
申请日：2005-10-27
申请人： Steven Clements , William Cornwell , Carrie Cox , Hayden Cranford , Todd Rasmus
发明人： Steven Clements , William Cornwell , Carrie Cox , Hayden Cranford , Todd Rasmus
IPC分类号： H03K19/003
CPC分类号： H03K17/164 , H03K19/018585 , H04L25/0272 , H04L25/0278 , H04L25/028
摘要： A circuit design method and transmitter that enables flexible control of amplitude, pre- emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control are enabled by manipulation/selection of normal or inverted inputs for the various segments. Also provided is a mechanism for providing/maintaining accurate output across a self-series terminated (SST) transmitter by regulating the supply voltage. Regulation of the supply voltage allows compatibility with conventional serial link receiver termination voltages and protects the transmitter output devices when those voltages are larger than the normal supply for the devices.
摘要翻译：一种电路设计方法和发射机，其利用具有双重上拉的多个单独可控段的并行配置的分段自串行终端（SSST）发射机的设计来灵活地控制幅度，预加重和转换速率，以及下拉晶体管。幅度控制，转换速率控制和预加重控制可以通过操作/选择各个段的正常或反相输入来实现。还提供了一种用于通过调节电源电压来提供/保持跨越自串式端接（SST）发射器的精确输出的机构。电源电压的调节允许与传统的串行链路接收器终端电压兼容，并在这些电压大于设备的正常供电时保护发射机输出设备。

2. 发明申请

US20070096720A1 Impedance calibration for source series terminated serial link transmitter 有权
标题翻译：源串联端接串行链路发射机的阻抗校准
公开(公告)号：US20070096720A1
公开(公告)日：2007-05-03
申请号：US11262101
申请日：2005-10-28
申请人： Steven Clements , William Cornwell , Carrie Cox , Hayden Cranford , Vernon Norman
发明人： Steven Clements , William Cornwell , Carrie Cox , Hayden Cranford , Vernon Norman
IPC分类号： G01R31/28
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译：将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

3. 发明申请

US20060245507A1 High speed serial link output stage having self adaptation for various impairments 失效
标题翻译：具有各种损伤的自适应的高速串行链路输出级
公开(公告)号：US20060245507A1
公开(公告)日：2006-11-02
申请号：US11119505
申请日：2005-04-29
申请人： Steven Clements , Carrie Cox , Hayden Cranford
发明人： Steven Clements , Carrie Cox , Hayden Cranford
IPC分类号： H04L25/00
CPC分类号： H04L25/0292 , H04L25/03885
摘要： A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.
摘要翻译：提供了一种高速串行链路结构和方法，包括数据驱动器和复制驱动器结构，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。

4. 发明申请

US20050105507A1 Power savings in serial link transmitters 失效
标题翻译：串行链路发射机节电
公开(公告)号：US20050105507A1
公开(公告)日：2005-05-19
申请号：US10697514
申请日：2003-10-30
申请人： Steven Clements , Carrie Cox , Hayden Cranford
发明人： Steven Clements , Carrie Cox , Hayden Cranford
IPC分类号： H03K17/16 , H03K19/00 , H04L25/02 , H04B1/26
CPC分类号： H04L25/028 , H03K17/163 , H03K17/164
摘要： Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.
摘要翻译：描述了在串行链路发射机中节省功率的方面。这些方面包括提供段的并行布置，每个段包括串行链路发射机的预缓冲器和输出级电路，并且每个段独立地使能实现多个功率电平和多级预加重，同时保持信号中基本恒定的传播延迟串行链路发射机的路径。另外的方面包括在预缓冲器级电路中提供旁路路径，以实现段中的可控空闲状态，并将预缓冲器电路中的尾电流和电阻负载元件作为转换速率控制能力的切片部分。还包括在发射机信号路径中提供具有预加重延迟电路的控制元件，以允许预加重延迟电路的最后延迟位的反转，以实现预加重权重的极性改变。

5. 发明申请

US20070096792A1 Transistor switch with integral body connection to prevent latchup 失效
公开(公告)号：US20070096792A1
公开(公告)日：2007-05-03
申请号：US11263008
申请日：2005-10-31
申请人： Hayden Cranford , Stacy Garvin , Todd Rasmus
发明人： Hayden Cranford , Stacy Garvin , Todd Rasmus
IPC分类号： H03K17/00
CPC分类号： H03K17/161 , H03K2217/0018
摘要： A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

6. 发明申请

US20050077936A1 Circuit and method for reducing jitter in a PLL of high speed serial links 失效
标题翻译：用于降低高速串行链路PLL的抖动的电路和方法
公开(公告)号：US20050077936A1
公开(公告)日：2005-04-14
申请号：US10685022
申请日：2003-10-14
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus
IPC分类号： H03L7/10 , H03L7/00
CPC分类号： H03L7/10
摘要： Aspects for reducing jitter in a PLL of a high speed serial link are described. The aspects include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.
摘要翻译：描述了降低高速串行链路的PLL抖动的方面。这些方面包括检查与PLL中的压控振荡器（VCO）的性能有关的至少一个参数，以及基于检查来控制对VCO的电源电压的调节。调节器控制电路进行检查和控制。

7. 发明申请

US20050046489A1 Self-adaptive voltage regulator for a phase-locked loop 失效
标题翻译：用于锁相环的自适应电压调节器
公开(公告)号：US20050046489A1
公开(公告)日：2005-03-03
申请号：US10650396
申请日：2003-08-28
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus , Peter Seidel
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus , Peter Seidel
IPC分类号： H03L7/08 , H03L7/00
CPC分类号： H03L7/08 , H03L2207/06
摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.
摘要翻译：公开了一种用于锁相环的自适应电压调节器。锁相环包括相位检测器，电荷泵，低通滤波器和压控振荡器，其中低通滤波器将控制电压输入到压控振荡器以产生输出时钟。根据本文公开的方法和系统，自适应电压调节器耦合到低通滤波器的输出，用于在锁相环的正常操作期间感测控制电压，并且用于动态调整供电电压，即响应于控制电压输入到压控振荡器，使得锁相环将控制电压保持在参考电压的预定范围内。

8. 发明申请

US20060267616A1 Systems and methods for controlling of electro-migration 有权
标题翻译：用于控制电迁移的系统和方法
公开(公告)号：US20060267616A1
公开(公告)日：2006-11-30
申请号：US11140765
申请日：2005-05-31
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译：公开了用于控制电迁移的系统和方法，并减少其有害影响。实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。

9. 发明申请

US20050127978A1 Electronic component value trimming systems 失效
标题翻译：电子元件修整系统
公开(公告)号：US20050127978A1
公开(公告)日：2005-06-16
申请号：US10967756
申请日：2004-10-18
申请人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
发明人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
IPC分类号： H01C17/22 , H03K3/00
CPC分类号： H01C17/22
摘要： Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.
摘要翻译：描述了一种用于修整电子部件的值的系统。该系统包括：至少一个修整部件，每个修剪部件具有相关联的开关，用于响应于控制矢量中的对应位选择性地将修剪部件连接到电子部件。如果电子部件的净值和任何连接的修整部件与期望值不同，则包括比较器以产生具有第一值的输出位。连接到开关和比较器的控制器根据比较器的输出产生控制向量，该控制器包括用于顺序地从比较器接收连续输出位的移位寄存器; 其中所述控制向量包括所述移位寄存器的内容，并且其中所述控制矢量中的所述第一值的位影响相应开关的切换。

10. 发明申请

US20080112521A1 Clock Data Recovering System with External Early/Late Input 有权
标题翻译：具有外部早/晚输入的时钟数据恢复系统
公开(公告)号：US20080112521A1
公开(公告)日：2008-05-15
申请号：US11966438
申请日：2007-12-28
申请人： Martin Schmatz , Hayden Cranford , Vernon Norman
发明人： Martin Schmatz , Hayden Cranford , Vernon Norman
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/089 , H04L7/0331
摘要： The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.
摘要翻译：本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。

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