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    • 1. 发明申请
    • Driver/equalizer with compensation for equalization non-idealities
    • 驱动器/均衡器补偿均衡非理想
    • US20060238237A1
    • 2006-10-26
    • US11103789
    • 2005-04-12
    • Steven ClementsCarrie CoxHayden Cranford,
    • Steven ClementsCarrie CoxHayden Cranford,
    • H04B1/10
    • H04L25/03885H04L25/0272H04L25/03343
    • A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output of a differential pair. When bit time>0, the error current is removed or subtracted from the total driver current, thereby maintaining a constant total current from bit time 0 to bit time>0. The same result can also be achieved by subtracting current when bit time>0 using field effect transistors of the opposite gender. The error current can be determined empirically from simulation or through feedback using a replica of the driver. The circuits for achieving equalization error correction and the resulting electrical network analysis are shown and described.
    • 高速串行数据通信系统包括用于校正均衡误差的规定,特别是由均衡器非理想性引入的错误。 在数据发射机上实现均衡,并且基于差分对的输出处的动态电流减法。 当位时间> 0时,误差电流从总驱动器电流中去除或减去,从而保持从位时间0到位时间> 0的恒定总电流。 通过使用相反性别的场效应晶体管减去位时间> 0时的电流,也可以实现相同的结果。 误差电流可以从仿真或使用驱动程序的副本通过反馈凭经验确定。 用于实现均衡纠错的电路和所得到的电网分析被显示和描述。
    • 5. 发明申请
    • Power savings in serial link transmitters
    • 串行链路发射机节电
    • US20050105507A1
    • 2005-05-19
    • US10697514
    • 2003-10-30
    • Steven ClementsCarrie CoxHayden Cranford
    • Steven ClementsCarrie CoxHayden Cranford
    • H03K17/16H03K19/00H04L25/02H04B1/26
    • H04L25/028H03K17/163H03K17/164
    • Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.
    • 描述了在串行链路发射机中节省功率的方面。 这些方面包括提供段的并行布置,每个段包括串行链路发射机的预缓冲器和输出级电路,并且每个段独立地使能实现多个功率电平和多级预加重,同时保持信号中基本恒定的传播延迟 串行链路发射机的路径。 另外的方面包括在预缓冲器级电路中提供旁路路径,以实现段中的可控空闲状态,并将预缓冲器电路中的尾电流和电阻负载元件作为转换速率控制能力的切片部分。 还包括在发射机信号路径中提供具有预加重延迟电路的控制元件,以允许预加重延迟电路的最后延迟位的反转,以实现预加重权重的极性改变。