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1. 发明申请

US20070069793A1 Method and system for high frequency clock signal gating 失效
标题翻译：高频时钟信号门控方法及系统
公开(公告)号：US20070069793A1
公开(公告)日：2007-03-29
申请号：US11235758
申请日：2005-09-27
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.
摘要翻译：提供了一种差分时钟信号门控方法和系统，其中时钟缓冲器电路控制路径产生与时钟信号的定时关系的时钟门控信号。时钟门控信号将响应于第一时钟信号脉冲负半部分的与时钟信号通信的时钟缓冲器电路控制路径上的缓冲器门控。缓冲器提供在第一时钟信号脉冲之后立即和顺序发生的第二和连续时钟信号脉冲，作为输出到第二级时钟路径中的第二缓冲级的缓冲时钟信号，每个具有标称时钟幅度和标称时钟脉冲宽度时钟信号无抖动。

2. 发明申请

US20070279117A1 METHOD AND SYSTEM FOR HIGH FREQUENCY CLOCK SIGNAL GATING 审中-公开
标题翻译：高频时钟信号增益的方法与系统
公开(公告)号：US20070279117A1
公开(公告)日：2007-12-06
申请号：US11769408
申请日：2007-06-27
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, providing a clock gating signal with a timing relationship to a clock signal and a differential pair current to a buffer differential pair load element. Switching the differential pair current from the load element to a buffer differential pair responsive to a gating signal pulse, the gating signal pulse correlated to a first clock signal pulse, the buffer differential pair buffers a second clock signal pulse occurring immediately and sequentially after the first clock signal pulse and successive clock signal pulses as a buffer clock signal output, the output comprising a plurality of pulses each having the clock signal amplitude and the clock signal pulse width.
摘要翻译：提供差分时钟信号门控方法和系统，提供具有与时钟信号的时序关系的时钟选通信号和到缓冲器差分对负载元件的差分对电流。响应于门控信号脉冲将差分对电流从负载元件切换到缓冲差分对，门控信号脉冲与第一时钟信号脉冲相关，缓冲差分对缓冲在第一时钟信号脉冲之后立即和顺序发生的第二时钟信号脉冲时钟信号脉冲和连续时钟信号脉冲作为缓冲时钟信号输出，所述输出包括多个脉冲，每个脉冲具有时钟信号幅度和时钟信号脉冲宽度。

3. 发明申请

US20050046489A1 Self-adaptive voltage regulator for a phase-locked loop 失效
标题翻译：用于锁相环的自适应电压调节器
公开(公告)号：US20050046489A1
公开(公告)日：2005-03-03
申请号：US10650396
申请日：2003-08-28
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus , Peter Seidel
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus , Peter Seidel
IPC分类号： H03L7/08 , H03L7/00
CPC分类号： H03L7/08 , H03L2207/06
摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.
摘要翻译：公开了一种用于锁相环的自适应电压调节器。锁相环包括相位检测器，电荷泵，低通滤波器和压控振荡器，其中低通滤波器将控制电压输入到压控振荡器以产生输出时钟。根据本文公开的方法和系统，自适应电压调节器耦合到低通滤波器的输出，用于在锁相环的正常操作期间感测控制电压，并且用于动态调整供电电压，即响应于控制电压输入到压控振荡器，使得锁相环将控制电压保持在参考电压的预定范围内。

4. 发明申请

US20070254613A1 Overshoot reduction in VCO calibration for serial link phase lock loop (PLL) 失效
标题翻译：用于串行链路锁相环（PLL）的VCO校准过程减少
公开(公告)号：US20070254613A1
公开(公告)日：2007-11-01
申请号：US11411662
申请日：2006-04-26
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman
IPC分类号： H04B7/00
CPC分类号： H03L7/18 , H03L7/0891
摘要： A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter nodes and thus centers the frequency of the VCO before stepping from one frequency band to the next.
摘要翻译：用于跟踪VCO校准的电路设计，方法和系统，而不需要如常规实现中的过度设计的分频器。滤波器复位分量被添加到VCO的输入端。在校准机构/过程中添加了一个处理步骤，该校准机构/过程使滤波器节点短路，并因此在从一个频带到下一个频带之前将VCO的频率居中。

5. 发明申请

US20060008042A1 Analog unidirectional serial link architecture 有权
标题翻译：模拟单向串行链路架构
公开(公告)号：US20060008042A1
公开(公告)日：2006-01-12
申请号：US11225600
申请日：2005-09-13
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Paul Owczarski , Martin Schmatz , Joseph Stevens
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Paul Owczarski , Martin Schmatz , Joseph Stevens
IPC分类号： H03D3/24
CPC分类号： H03L7/0995 , H04L7/0004 , H04L7/0337
摘要： The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
摘要翻译：本发明涉及包括逻辑发射机部分和逻辑接收机部分的统一数字架构。提供了一种用于在包括发射机和接收机部分的有线媒体上传输数字数据的统一的串行链路系统和方法，发射机部分和接收机部分之一包括锁相环（PLL）电路。 PLL电路包括压控振荡器，分频器，相频检测器，电荷泵和多极环路滤波器。一个实施例包括具有数字粗略回路和模拟精细回路的双回路PLL。

6. 发明申请

US20050077936A1 Circuit and method for reducing jitter in a PLL of high speed serial links 失效
标题翻译：用于降低高速串行链路PLL的抖动的电路和方法
公开(公告)号：US20050077936A1
公开(公告)日：2005-04-14
申请号：US10685022
申请日：2003-10-14
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus
IPC分类号： H03L7/10 , H03L7/00
CPC分类号： H03L7/10
摘要： Aspects for reducing jitter in a PLL of a high speed serial link are described. The aspects include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.
摘要翻译：描述了降低高速串行链路的PLL抖动的方面。这些方面包括检查与PLL中的压控振荡器（VCO）的性能有关的至少一个参数，以及基于检查来控制对VCO的电源电压的调节。调节器控制电路进行检查和控制。

7. 发明申请

US20070096792A1 Transistor switch with integral body connection to prevent latchup 失效
公开(公告)号：US20070096792A1
公开(公告)日：2007-05-03
申请号：US11263008
申请日：2005-10-31
申请人： Hayden Cranford , Stacy Garvin , Todd Rasmus
发明人： Hayden Cranford , Stacy Garvin , Todd Rasmus
IPC分类号： H03K17/00
CPC分类号： H03K17/161 , H03K2217/0018
摘要： A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

8. 发明申请

US20080112521A1 Clock Data Recovering System with External Early/Late Input 有权
标题翻译：具有外部早/晚输入的时钟数据恢复系统
公开(公告)号：US20080112521A1
公开(公告)日：2008-05-15
申请号：US11966438
申请日：2007-12-28
申请人： Martin Schmatz , Hayden Cranford , Vernon Norman
发明人： Martin Schmatz , Hayden Cranford , Vernon Norman
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/089 , H04L7/0331
摘要： The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.
摘要翻译：本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。

9. 发明申请

US20060209944A1 Altering power consumption in communication links based on measured noise 有权
公开(公告)号：US20060209944A1
公开(公告)日：2006-09-21
申请号：US11079952
申请日：2005-03-15
申请人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Brian Schuh
发明人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Brian Schuh
IPC分类号： H04B17/00 , H03D1/04
CPC分类号： H04B17/382 , H04B17/24 , H04B17/345
摘要： A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.

10. 发明申请

US20050195863A1 Circuit and method for providing automatic adaptation to frequency offsets in high speed serial links 有权
标题翻译：用于在高速串行链路中提供自动适应频率偏移的电路和方法
公开(公告)号：US20050195863A1
公开(公告)日：2005-09-08
申请号：US10791175
申请日：2004-03-02
申请人： Hayden Cranford , Gareth Nicholls , Bobak Modaress-Razavi , Vernon Norman , Martin Schmatz
发明人： Hayden Cranford , Gareth Nicholls , Bobak Modaress-Razavi , Vernon Norman , Martin Schmatz
IPC分类号： H03L7/07 , H03L7/081 , H03L7/093 , H04L27/00 , H04J3/06
CPC分类号： H03L7/0814 , H03L7/07 , H04L2027/0065 , H04L2027/0067
摘要： Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
摘要翻译：描述了在高速串行链路中提供对频偏的自动适配的方面。通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。耦合到加法器的组合逻辑基于累积数据来适配信号。

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