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21. 发明公开

KR1020110129256A 반도체 소자 및 그 제조 방법 有权
标题翻译：半导体及其制造方法
公开(公告)号：KR1020110129256A
公开(公告)日：2011-12-01
申请号：KR1020100048795
申请日：2010-05-25
申请人： 삼성전자주식회사
发明人： 황성민 , 김경훈 , 김한수 , 손병근 , 심재주 , 장재훈 , 조원석 , 조후성
IPC分类号： H01L27/10 , H01L21/70 , H01L27/115 , H01L21/8247
CPC分类号： H01L27/0688 , H01L21/76816 , H01L27/10885 , H01L27/10891 , H01L27/11551 , H01L27/11578
摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to stably supply voltage on a substrate through a pickup area which is electrically connected to the substrate, thereby making the semiconductor device with excellent reliability. CONSTITUTION: A substrate(100) is doped with a first conductive type dopant. A plurality of laminate structures is extended side by side to a first direction on the substrate. Each laminate structure comprises gate electrodes(157L,157,157U) which is laminated by being separated from each other on the substrate. A plurality of laminate structures comprises a pair of the laminate structures which is perpendicular to the first direction and separated with a first interval to a second direction. A pickup region(176) is extended to the first direction within the substrate between the pair of the laminated structures and doped with the first conductive type dopant.
摘要翻译：目的：提供半导体器件及其制造方法，通过与基板电连接的拾取区域稳定地在基板上提供电压，从而使半导体器件具有良好的可靠性。构成：衬底（100）掺杂有第一导电型掺杂剂。多个层压结构在基板上沿第一方向并排延伸。每个层压结构包括通过在基板上彼此分离而层压的栅电极（157L，157,157U）。多个层叠结构包括一对垂直于第一方向并且以第一间隔分离成第二方向的层压结构。拾取区域（176）在衬底之间的第一方向延伸到一对层压结构之间并掺杂有第一导电型掺杂剂。

22. 发明公开

KR1020110126999A 반도체 소자 및 그 제조 방법 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020110126999A
公开(公告)日：2011-11-24
申请号：KR1020100046593
申请日：2010-05-18
申请人： 삼성전자주식회사
发明人： 황성민 , 김한수 , 조원석 , 장재훈 , 심재주
IPC分类号： H01L27/115 , H01L27/02
CPC分类号： H01L27/0207 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： PURPOSE: A semiconductor device and a method of fabricating the same are provided to minimize an over etching due to the height difference between contact holes by forming a reserved contact hole through a barrier rip. CONSTITUTION: In a semiconductor device and a method of fabricating the same, a substrate(100) comprises a first area(10) and a second area(20). A pattern structure including each pattern(108) is arranged on the substrate within the first area. A conductive pattern(CP) is arranged on the substrate within the second area. The conductive patterns includes a connection unit connecting a plurality of gate electrodes and one end of a gate electrode. A semiconductor pillar(130) comprises a semiconductor(131), a filling insulating material(132), and a drain(133).
摘要翻译：目的：提供一种半导体器件及其制造方法，以通过形成通过阻挡层的保留接触孔来最小化由于接触孔之间的高度差引起的过度蚀刻。构成：在半导体器件及其制造方法中，衬底（100）包括第一区域（10）和第二区域（20）。包括每个图案（108）的图案结构布置在第一区域内的基板上。导电图案（CP）布置在第二区域内的基板上。导电图案包括连接多个栅电极和栅电极的一端的连接单元。半导体柱（130）包括半导体（131），填充绝缘材料（132）和漏极（133）。

23. 发明公开

KR1020110070142A 3차원 반도체 장치 및 그 제조 방법 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：KR1020110070142A
公开(公告)日：2011-06-24
申请号：KR1020090126854
申请日：2009-12-18
申请人： 삼성전자주식회사
发明人： 심재주 , 김한수 , 조원석 , 장재훈 , 조우진
IPC分类号： H01L21/822 , H01L21/027 , H01L21/28
CPC分类号： H01L23/3157 , H01L21/76816 , H01L23/291 , H01L23/528 , H01L27/11519 , H01L27/11521 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , G03F7/0002 , G03F7/0037 , H01L2924/00
摘要： PURPOSE: A three dimensional semiconductor device and manufacturing method thereof are provided to prevent deformation of a mold structure by sidewall molds, thereby obtaining structural stability without a separate support object. CONSTITUTION: A mold structure provides gap areas. The mold structure includes interlayer molds and sidewall molds. The interlayer molds(110) define the upper surface and the lower surface of wiring patterns. The sidewall molds(130) define sidewalls of the wiring patterns under the interlayer molds. A wiring structure comprises a plurality of wiring patterns arranged in the gap areas.
摘要翻译：目的：提供一种三维半导体器件及其制造方法，以防止侧壁模具对模具结构的变形，从而在没有单独的支撑体的情况下获得结构稳定性。规定：模具结构提供了间隙区域。模具结构包括层间模具和侧壁模具。层间模具（110）限定布线图案的上表面和下表面。侧壁模具（130）限定层间模具下面的布线图案的侧壁。布线结构包括布置在间隙区域中的多个布线图案。

24. 发明公开

KR1020110054361A 3차원 반도체 기억 소자 有权
标题翻译：三维半导体存储器件
公开(公告)号：KR1020110054361A
公开(公告)日：2011-05-25
申请号：KR1020090110975
申请日：2009-11-17
申请人： 삼성전자주식회사
发明人： 심선일 , 허성회 , 김한수 , 장재훈 , 조후성
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/02365 , H01L21/02697 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/7841
摘要： PURPOSE: A three dimensional semiconductor memory device is provided to operate at high speed and improve reliability by decreasing resistance between sub gates. CONSTITUTION: A substrate has a pair of sub cell regions and a cell array region including a strapping region. A plurality of sub gates(135a,135au,135b,135bu) are successively laminated in each sub cell region. Each sub gate has an extension unit which is extended in the strapping region. A vertical type channel pattern successively passes through the sub gates laminated in each sub cell region. The wirings are electrically connected to the extension units of the sub gates. Each wire is arranged in the pair of sub cell regions and is electrically connected to the extension units of the pair of sub gates on the same level.
摘要翻译：目的：提供三维半导体存储器件，通过降低子门之间的电阻，高速运行并提高可靠性。构成：衬底具有一对子电池区域和包括带状区域的电池阵列区域。多个子门（135a，135au，135b，135bu）依次层叠在每个子单元区域中。每个子门具有在捆扎区域中延伸的延伸单元。垂直型通道图案依次通过层叠在每个子单元区域中的子门。配线电连接到子门的延伸单元。每根导线布置在一对子单元区域中，并且与同一电平上的一对子门的延伸单元电连接。

25. 发明公开

KR1020110029403A 3차원 반도체 메모리 장치 및 그 제조 방법 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：KR1020110029403A
公开(公告)日：2011-03-23
申请号：KR1020090087063
申请日：2009-09-15
申请人： 삼성전자주식회사
发明人： 심선일 , 장재훈 , 김한수 , 황성민 , 조원석 , 임진수
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L29/7926 , H01L27/11556 , H01L27/11582
摘要： PURPOSE: A three dimensional semiconductor memory device and a manufacturing method thereof are provided to restrain the non-uniformity in the electrical characteristic between the memory cells by forming the lower and upper semiconductor patterns using the same material without discontinuous boundary. CONSTITUTION: A lower part thin film structure(100) is formed on a substrate(10). The lower part thin film structure comprises a plurality of bottom insulating layers(121~127) and a plurality of lower part sacrificing layers(131~136). A lower penetration hole(140) passes through the lower part thin film structure. A bottom semiconductor pattern(150) fills the lower penetration holes.
摘要翻译：目的：提供三维半导体存储器件及其制造方法，以通过使用相同材料形成下部和上部半导体图案来不间断地限制存储单元之间的电气特性的不均匀性。构成：在基板（10）上形成下部薄膜结构（100）。下部薄膜结构包括多个底部绝缘层（121〜127）和多个下部牺牲层（131〜136）。下穿孔（140）穿过下部薄膜结构。底部半导体图案（150）填充下部穿透孔。

26. 发明公开

KR1020110021444A 3차원 반도체 메모리 장치 및 그 제조 방법 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：KR1020110021444A
公开(公告)日：2011-03-04
申请号：KR1020090079243
申请日：2009-08-26
申请人： 삼성전자주식회사
发明人： 손병근 , 김한수 , 안영수 , 김민구 , 김진호 , 최재형 , 최석헌
IPC分类号： H01L27/115
CPC分类号： H01L27/11575 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L27/0688 , H01L21/76897 , H01L27/2463 , H01L2924/00
摘要： PURPOSE: A 3d semiconductor memory apparatus and a manufacturing method thereof are provided to obtain the forming margin of a contact plugs or wirings directly connected to the contact extensions by arranging the contact extensions and the even conductive patterns on the different contact areas. CONSTITUTION: A substrate(10) comprises a cell array region(CAR) and contact areas(CR1, CR2). An extrusion oxide(11) is arranged on the contact area of the substrate. A plurality of conductive patterns(GL1~GL6) is deposited with an interval on the substrate. The conductive pattern comprises a wire portion(IC) which is parallel to the substrate and a contact extension part(CT) being tilted to the substrate.
摘要翻译：目的：提供3d半导体存储装置及其制造方法，以通过将接触延伸部和偶数导电图案布置在不同的接触区域上来获得直接连接到接触延伸部的接触插塞或布线的成形边缘。构成：衬底（10）包括电池阵列区（CAR）和接触区（CR1，CR2）。挤出氧化物（11）设置在基板的接触区域上。多个导电图案（GL1〜GL6）在衬底上以间隔沉积。导电图案包括平行于基板的导线部分（IC）和向基板倾斜的接触延伸部分（CT）。

27. 发明授权

KR100991220B1 접착된 계면을 갖는 기판 내의 콘택 구조체, 이를 구비하는반도체 소자 및 이를 제조하는 방법들 失效
标题翻译：具有接合界面的基板中的接触结构，包括该接合界面的半导体器件及其制造方法
公开(公告)号：KR100991220B1
公开(公告)日：2010-11-04
申请号：KR1020080070716
申请日：2008-07-21
申请人： 삼성전자주식회사
发明人： 송민성 , 정순문 , 김한수 , 나영섭 , 조원석 , 손양수 , 김종혁 , 장영철
IPC分类号： H01L21/28
CPC分类号： H01L27/11519 , G11C5/02 , G11C16/0483 , H01L21/76898 , H01L23/481 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： 접착 계면을 관통하는 콘택 구조체가 제공된다. 상기 콘택 구조체는 하부 기판 상의 하부 절연층 및 상기 하부 절연층 상의 상부 기판을 구비한다. 상기 상부 기판을 관통하여 상기 하부 절연층 내로 연장하는 그루브가 배치된다. 상기 그루브는 상기 상부 기판 및 상기 하부 절연층 사이의 계면보다 낮은 바닥면을 갖는다. 상기 그루브는 상부 절연층으로 채워진다. 상기 그루브 내의 상기 상부 절연층을 관통하여 상기 하부 절연층 내로 연장하는 콘택 플러그가 배치된다. 상기 콘택 구조체의 형성방법 또한 제공된다.

28. 发明公开

KR1020100112862A 비휘발성 메모리 장치 有权
标题翻译：非易失性存储器件
公开(公告)号：KR1020100112862A
公开(公告)日：2010-10-20
申请号：KR1020090031368
申请日：2009-04-10
申请人： 삼성전자주식회사
发明人： 정재훈 , 김한수 , 장재훈 , 조후성 , 김경훈
IPC分类号： H01L27/115 , G11C16/02
CPC分类号： H01L27/11578 , H01L27/115 , H01L27/11517 , H01L27/11565 , H01L27/11582 , G11C16/02 , H01L21/76897 , H01L27/0207 , H01L27/0688
摘要： PURPOSE: A nonvolatile memory device is provided to form a word line without disconnection by forming cell arrays with a separated structure to provide a space for strapping a common source region or/and well region. CONSTITUTION: A first cell array(130a) and a second cell array(130b) are arranged on a semiconductor substrate. A common source region is formed on the semiconductor substrate under semiconductor patterns. A first impurity region electrically connects the common source regions. A first contact hole expose the part of the first impurity region between the separated cell arrays. Common source lines(170S) and well lines(170W) are formed on contact plugs.
摘要翻译：目的：提供非易失性存储器件，以通过形成具有分离结构的单元阵列来形成字线而不断开以提供用于捆扎公共源区域或/和阱区域的空间。构成：第一电池阵列（130a）和第二电池阵列（130b）布置在半导体衬底上。在半导体图案下的半导体衬底上形成公共源极区域。第一杂质区域电连接共同的源极区域。第一接触孔暴露分离的电池阵列之间的第一杂质区域的一部分。公共源极线（170S）和阱线（170W）形成在接触插塞上。

29. 发明公开

KR1020100109745A 반도체 장치 및 그 형성 방법 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：KR1020100109745A
公开(公告)日：2010-10-11
申请号：KR1020090028159
申请日：2009-04-01
申请人： 삼성전자주식회사
发明人： 심재주 , 김한수 , 조원석 , 심선일 , 임주영
IPC分类号： H01L21/82
摘要： PURPOSE: The semiconductor device and formation method the semiconductor device with a superior quality the peripheral circuit is formed on the spark region and formation method can be offered. The opening having the high level difference offers the removed semiconductor device and a method of formation thereof and the quality excellent. CONSTITUTION: The semiconductor device and formation method comprises the recess region(106) and the spark region(108) including the floor side and side are formed on the semiconductor substrate. Plateau on the floor side of the recess region and the sidewall part expanded from plateau as the side are included.
摘要翻译：目的：半导体器件和形成方法是具有优异质量的半导体器件，外围电路形成在火花区域上，并且可以提供形成方法。具有高电平差的开口提供了去除的半导体器件及其形成方法，并且质量优异。构成：半导体器件和形成方法包括凹部区域（106），并且包括地板侧和侧面的火花区域（108）形成在半导体衬底上。包括在凹部区域的地板侧的高原以及从侧面扩张的侧壁部分。

30. 发明授权

KR100971532B1 구동 트랜지스터를 포함하는 반도체 소자 有权
标题翻译：一个驱动晶体管的半导体器件
公开(公告)号：KR100971532B1
公开(公告)日：2010-07-21
申请号：KR1020080049219
申请日：2008-05-27
申请人： 삼성전자주식회사
发明人： 윤종인 , 정순문 , 김한수 , 장재훈 , 조후성 , 박준범 , 정재훈
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/8221 , H01L27/0688 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： 본 발명은 구동 트랜지스터를 포함하는 반도체 소자를 제공한다. 이 소자는 기판 상에 차례로 적층된 절연막 및 반도체막, 및 반도체막 내에 형성되어 반도체 패턴을 정의하는 격리 트렌치를 채우는 소자분리막을 포함한다. 고전압을 제어하는 구동 트랜지스터가 반도체 패턴에 형성되고, 격리 트렌치의 바닥면은 절연막의 상부면의 일부이다.

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