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21. 发明授权

US5214296A Thin-film semiconductor device and method of fabricating the same 失效
标题翻译：薄膜半导体器件及其制造方法
公开(公告)号：US5214296A
公开(公告)日：1993-05-25
申请号：US848840
申请日：1992-03-10
申请人： Yoshiro Nakata , Naoto Matsuo , Toshiki Yabu , Susumu Matsumoto , Shozo Okada
发明人： Yoshiro Nakata , Naoto Matsuo , Toshiki Yabu , Susumu Matsumoto , Shozo Okada
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78642 , H01L27/10817
摘要： A thin-film semiconductor device having a vertical TFT which includes a gate insulating film formed on a sidewall of a throughhole formed in an insulating layer; a thin-film semiconductor layer formed on the gate insulating film; and a gate electrode formed within the insulating layer. The gate electrode, the gate insulating film, and the thin-film semiconductor layer together form a lateral MOS structure. The thin-film semiconductor layer is connected to a bit line at the bottom of the throughhole and to a storage node of a capacitor formed over the switching transistor.
摘要翻译：一种具有垂直TFT的薄膜半导体器件，其包括形成在绝缘层中形成的通孔的侧壁上的栅极绝缘膜; 形成在所述栅极绝缘膜上的薄膜半导体层; 以及形成在所述绝缘层内的栅电极。栅电极，栅极绝缘膜和薄膜半导体层一起形成横向MOS结构。薄膜半导体层连接到通孔底部的位线和形成在开关晶体管上的电容器的存储节点。

22. 发明授权

US5892368A Semiconductor integrated circuit device having failure detection circuitry 失效
标题翻译：具有故障检测电路的半导体集成电路装置
公开(公告)号：US5892368A
公开(公告)日：1999-04-06
申请号：US744082
申请日：1996-11-04
申请人： Yoshiro Nakata , Shin Hashimoto , Isao Miyanaga
发明人： Yoshiro Nakata , Shin Hashimoto , Isao Miyanaga
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/2884 , G01R31/2849
摘要： A 12.5-MHz signal is applied from outside a semiconductor integrated circuit (SIC) device to a signal input terminal of that SIC device. A frequency multiplying circuit is fed that 12.5-MHz signal from the input terminal, and delivers a reference signal whose frequency is a multiple of the frequency of the signal received (i.e., 100 MHz), to a semiconductor memory and to a self-test circuit. The self-test circuit provides a test signal in synchronism with that 100-MHz reference signal to the semiconductor memory for testing for the presence or absence of a failure. All elements of the semiconductor memory are tested by the self-test circuit for a failure. If the self-test circuit finds a semiconductor memory element that fails to work properly, it provides a signal indicative of such failure to a failure counting circuit. This failure counting circuit counts the number of times the self-test circuit provides such a signal.
摘要翻译：从半导体集成电路（SIC）器件外部向该SIC器件的信号输入端施加12.5MHz信号。馈送来自输入端的12.5MHz信号的倍频电路，并将其频率为接收信号的频率（即100MHz）的倍数的参考信号传送到半导体存储器并进行自检电路。自测电路与该半导体存储器的100MHz参考信号同步地提供测试信号，以测试是否存在故障。半导体存储器的所有元件都通过自检电路进行故障测试。如果自检电路发现无法正常工作的半导体存储器元件，则向故障计数电路提供指示这种故障的信号。该故障计数电路对自检电路提供这种信号的次数进行计数。

23. 发明授权

US5665610A Semiconductor device checking method 失效
标题翻译：半导体器件检查方法
公开(公告)号：US5665610A
公开(公告)日：1997-09-09
申请号：US650486
申请日：1996-05-17
申请人： Yoshiro Nakata , Shinichi Oki , Koichi Nagao , Kenzo Hatada , Shigeoki Mori , Takashi Sato , Kunio Sano
发明人： Yoshiro Nakata , Shinichi Oki , Koichi Nagao , Kenzo Hatada , Shigeoki Mori , Takashi Sato , Kunio Sano
IPC分类号： G01R31/28 , H01L21/66
CPC分类号： G01R31/2884 , G01R31/2831
摘要： A plated layer made of a metal which is hard to oxidize is formed on the surface of a check electrode of a semiconductor chip which is formed on a semiconductor wafer. A bump of a contactor is caused to come in contact with the check electrode on which the plated layer is formed in the direction perpendicular to the semiconductor chip. Then, a voltage is applied to the bump of the contactor to make a check such as burn-in on the semiconductor chip in a lump.
摘要翻译：在形成在半导体晶片上的半导体芯片的检查电极的表面上形成由难以氧化的金属制成的镀层。使接触器的凸起与垂直于半导体芯片的方向上形成有镀层的检查电极接触。然后，向接触器的凸起施加电压，以一次性地对半导体芯片进行诸如老化的检查。

24. 发明授权

US5315543A Semiconductor memory device and a manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5315543A
公开(公告)日：1994-05-24
申请号：US882064
申请日：1992-05-12
申请人： Naoto Matsuo , Hisashi Ogawa , Yoshiro Nakata , Shozo Okada
发明人： Naoto Matsuo , Hisashi Ogawa , Yoshiro Nakata , Shozo Okada
IPC分类号： H01L27/108 , G11C13/00
CPC分类号： H01L27/10829
摘要： A semiconductor memory device includes a single crystalline semiconductor substrate having a main surface, a plurality of active regions formed at the main surface, and an isolation region which is formed at the main surface and isolates the active regions from one another. Each of the active regions has a transistor region and a capacitor region. The capacitor region has a trench formed in the single crystalline semiconductor substrate. An inner wall of the trench is covered with an insulating layer. At least a portion of the transistor region and the insulating layer are both covered with a semiconductor layer. A portion of the semiconductor layer which covers at least the portion of the transistor region is an epitaxial layer. A portion of the semiconductor layer which covers the insulating layer is a polycrystalline layer, which functions as a storage node of a capacitor. A semiconductor memory device is manufactured by forming an isolation region for isolating a plurality of active regions from one another at a main surface of a single crystalline semiconductor substrate, forming a trench in at least a portion of the active regions of the single crystalline semiconductor substrate, covering an inner wall of the trench with an insulating layer, forming a polysilicon seed film on the insulating layer, and growing a single crystalline silicon layer and a polysilicon layer respectively on an exposed portion of the top surface of the single crystalline semiconductor substrate and on the polysilicon seed film simultaneously and selectively.
摘要翻译：半导体存储器件包括具有主表面，形成在主表面上的多个有源区的单晶半导体衬底和形成在主表面处的隔离区，并且将有源区彼此隔离。每个有源区具有晶体管区和电容区。电容器区域具有在单晶半导体衬底中形成的沟槽。沟槽的内壁被绝缘层覆盖。晶体管区域和绝缘层的至少一部分都被半导体层覆盖。覆盖晶体管区域的至少一部分的半导体层的一部分是外延层。覆盖绝缘层的半导体层的一部分是用作电容器的存储节点的多晶层。半导体存储器件通过在单晶半导体衬底的主表面上形成用于隔离多个有源区彼此的隔离区域而形成，在单晶半导体衬底的至少一部分有源区中形成沟槽用绝缘层覆盖沟槽的内壁，在绝缘层上形成多晶硅种子膜，分别在单晶半导体衬底的顶表面的暴露部分上生长单晶硅层和多晶硅层，以及同时和选择性地在多晶硅种子膜上。

25. 发明授权

US5248936A Semiconductor integrated circuit and a method of testing the same 失效
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US5248936A
公开(公告)日：1993-09-28
申请号：US767998
申请日：1991-09-30
申请人： Yoshiro Nakata , Atsushi Fujiwara , Akinori Shibayama
发明人： Yoshiro Nakata , Atsushi Fujiwara , Akinori Shibayama
IPC分类号： H01L27/10 , G01R31/28 , H01L21/66
CPC分类号： G01R31/2884
摘要： A semiconductor integrated circuit has a main circuit (1), a self testing circuit (2) for testing the main circuit (1), a test start signal detection circuit (5) having at least one light sensitive device for detecting a test start signal in the form of light, and a test result output circuit (4) having at least one light emitting device for outputting test results from the self testing circuit (2) in the form of light. A drastic reduction in test time is accomplished by applying the test start signal in a non-contacting manner to the semiconductor integrated circuit so as to activate the self testing circuit. Furthermore, the test result is output to the outside of the semiconductor integrated circuit without having to provide electrical connections, and the simultaneous testing of a greater number of semiconductor integrated circuits as formed on the same wafer can be accomplished.
摘要翻译：半导体集成电路具有主电路（1），用于测试主电路（1）的自检电路（2），具有至少一个用于检测测试开始信号的光敏装置的测试开始信号检测电路（5）以及具有至少一个发光装置的测试结果输出电路（4），用于以光的形式从自检电路（2）输出测试结果。通过将测试开始信号以非接触的方式施加到半导体集成电路以激活自检电路来实现测试时间的急剧减少。此外，测试结果输出到半导体集成电路的外部，而不必提供电连接，并且可以实现在同一晶片上形成的更多数量的半导体集成电路的同时测试。

26. 发明授权

US5006717A Method of evaluating a semiconductor device and an apparatus for performing the same 失效
标题翻译：半导体装置的评价方法及其执行装置
公开(公告)号：US5006717A
公开(公告)日：1991-04-09
申请号：US456994
申请日：1989-12-26
申请人： Noriko Tsutsu , Yoshiro Nakata , Hideya Esaki
发明人： Noriko Tsutsu , Yoshiro Nakata , Hideya Esaki
IPC分类号： G01N21/66 , G01R31/265
CPC分类号： G01N21/66 , G01R31/2656 , G01N2021/6421 , G01N21/6458
摘要： A method and apparatus for evaluating the lifetime of a semiconductor device are disclosed. Luminescence of a predetermined wavelength which is emitted from an operating semiconductor device is detected. The luminescence of the predetermined wavelength is one which correlates with the degradation of the semiconductor device. Then, the image of detected luminescence of the predetermined wavelength is processed to determine the place of the degradation caused by hot carriers.
摘要翻译：公开了一种用于评估半导体器件寿命的方法和装置。检测从操作半导体器件发出的预定波长的发光。预定波长的发光是与半导体器件的劣化相关的发光。然后，对预定波长的检测到的发光的图像进行处理，以确定由热载体引起的劣化的位置。

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