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21. 发明申请

US20160027787A1 PADS INCLUDING CURVED SIDES AND RELATED ELECTRONIC DEVICES, STRUCTURES, AND METHODS 审中-公开
标题翻译：包括曲面和相关电子设备，结构和方法
公开(公告)号：US20160027787A1
公开(公告)日：2016-01-28
申请号：US14847324
申请日：2015-09-08
申请人： Je-Min Park , Seok-Hyun Lim , Tae-Yong Song , Hyun-Chul Yoon , Yoo-Sang Hwang , Hyeon-Ok Jung
发明人： Je-Min Park , Seok-Hyun Lim , Tae-Yong Song , Hyun-Chul Yoon , Yoo-Sang Hwang , Hyeon-Ok Jung
IPC分类号： H01L27/108 , H01L21/3213
CPC分类号： H01L27/10855 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76895 , H01L21/76897 , H01L27/1085 , H01L27/10885 , H01L27/10894 , H01L27/10897
摘要： An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.
摘要翻译：电子器件可以包括衬底和衬底上的多个间隔开的衬垫。每个垫可以包括第一，第二，第三和第四侧，第一和第三侧可以是基本上直的相对侧，并且第二和第四侧可以是相对的弯曲的侧面。还讨论了相关方法，设备和结构。

22. 发明申请

US20160020251A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：磁性随机访问存储器件及其制造方法
公开(公告)号：US20160020251A1
公开(公告)日：2016-01-21
申请号：US14724725
申请日：2015-05-28
申请人： Eun-Jung KIM , Se-Myeong JANG , Dae-Ik KIM , Je-Min PARK , Yoo-Sang HWANG
发明人： Eun-Jung KIM , Se-Myeong JANG , Dae-Ik KIM , Je-Min PARK , Yoo-Sang HWANG
IPC分类号： H01L27/22 , H01L43/08 , H01L29/78 , H01L43/02
CPC分类号： H01L27/228 , H01L29/7827 , H01L43/08
摘要： An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other. MTJ structures may be electrically connected to corresponding ones of the second semiconductor patterns. Each bit line structure may electrically connect two adjacent MTJ structures in the first direction to each other.
摘要翻译： MRAM器件可以包括布置在衬底上的半导体结构，公共源极区，漏极区，沟道区，栅极结构，字线结构，MTJ结构和位线结构。每个半导体结构可以包括具有基本上线性形状的第一半导体图案，该第一半导体图案沿着基本上平行于基板的顶表面的第一方向延伸，以及多个第二图案，每个第二图案沿基本上垂直于基板的第三方向延伸衬底的顶表面。可以在每个半导体结构中形成公共源极区域和漏极区域，以在第三方向上彼此间隔开，并且沟道区域可以布置在公共源极区域和漏极区域之间。可以在相邻的第二半导体图案之间沿第二方向形成栅极结构。字线结构可以将布置在第一方向上的栅极结构彼此电连接。 MTJ结构可以电连接到相应的第二半导体图案。每个位线结构可以将第一方向上的两个相邻的MTJ结构彼此电连接。

23. 发明授权

US08766354B2 Semiconductor devices including vertical channel transistors and methods of manufacturing the same 有权
标题翻译：包括垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08766354B2
公开(公告)日：2014-07-01
申请号：US13185961
申请日：2011-07-19
申请人： Hyun-woo Chung , Hyeong-sun Hong , Yong-chul Oh , Yoo-sang Hwang , Cheol-ho Baek , Kang-uk Kim
发明人： Hyun-woo Chung , Hyeong-sun Hong , Yong-chul Oh , Yoo-sang Hwang , Cheol-ho Baek , Kang-uk Kim
IPC分类号： H01L29/66
CPC分类号： H01L27/10876 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches.
摘要翻译：一种半导体器件，包括沿第一方向延伸的多个掩埋字线和沿第二方向延伸的多个掩埋位线。多个掩埋字线和多个掩埋位线的上表面比衬底的上表面低。构成第一组有源区域中的多个第一有源区域中的构成一对第一有源区域的两个有源区域之间的距离小于其间具有多个掩埋位线的两个相邻有源区域之间的距离。一种制造半导体器件的方法包括在衬底中形成多个第一沟槽，在多个第一沟槽中形成多个第一导电图案，使得一对第一导电图案设置在多个第一沟槽中的每一个中第一沟槽，在所述多个第一沟槽中形成多个第一掩埋图案以覆盖所述多个第一导电图案，通过在所述多个第一沟槽之间蚀刻所述衬底形成多个第二沟槽，以及形成多个第二掩埋图案在多个第二沟槽中。

24. 发明授权

US08742493B2 Semiconductor devices having vertical channel transistors and methods for fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08742493B2
公开(公告)日：2014-06-03
申请号：US13285263
申请日：2011-10-31
申请人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
发明人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
IPC分类号： H01L27/108
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/1033 , H01L29/1087 , H01L29/66666 , H01L29/7831
摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.
摘要翻译：半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

25. 发明申请

US20140061736A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140061736A1
公开(公告)日：2014-03-06
申请号：US14018709
申请日：2013-09-05
申请人： YOO-SANG HWANG , HYUN-WOO CHUNG , DAE-IK KIM
发明人： YOO-SANG HWANG , HYUN-WOO CHUNG , DAE-IK KIM
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/49811 , H01L21/76229 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/522 , H01L23/5222 , H01L23/53295 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces.
摘要翻译：半导体器件包括导电线的堆叠结构和在衬底上沿第一方向延伸的绝缘覆盖线，沿着第一方向排列成一排的多个接触插塞，并且具有面向导电线的侧壁表面，侧壁表面和导电线，以及插入在绝缘封盖线和接触塞之间的支撑件，以限制空气空间的高度。支撑件的宽度变化，或支撑件仅在第一方向间歇地存在。在制造半导体器件的方法中，在堆叠结构的侧面上形成牺牲隔离物，间隔物凹陷，在凹部中形成支撑层，蚀刻支承层以形成载体，然后将其余部分的间隔件被移除以提供空气空间。

26. 发明授权

US08552472B2 Integrated circuit devices including vertical channel transistors with shield lines interposed between bit lines and methods of fabricating the same 有权
标题翻译：集成电路器件，包括垂直沟道晶体管，屏蔽线插入位线之间，以及制造它们的方法
公开(公告)号：US08552472B2
公开(公告)日：2013-10-08
申请号：US13155688
申请日：2011-06-08
申请人： Hui-jung Kim , Yong-chul Oh , Yoo-sang Hwang , Hyun-woo Chung
发明人： Hui-jung Kim , Yong-chul Oh , Yoo-sang Hwang , Hyun-woo Chung
IPC分类号： H01L27/10 , H01L29/778 , H01L27/105
CPC分类号： H01L29/7788 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/7827
摘要： An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.
摘要翻译：集成电路装置包括沿着第一方向从基板突出的多个支柱。每个支柱包括在其相对端的源极/漏极区域和在源极/漏极区域之间延伸的沟道区域。多个导电位线在基本上垂直于第一方向的第二方向上在基板上邻近柱子延伸。多个导电屏蔽线在第二方向上在基板上延伸，使得每个屏蔽线在相邻的位线之间延伸。还讨论了相关的制造方法。

27. 发明授权

US08497174B2 Method of fabricating semiconductor device including vertical channel transistor 有权
标题翻译：制造包括垂直沟道晶体管的半导体器件的方法
公开(公告)号：US08497174B2
公开(公告)日：2013-07-30
申请号：US13240135
申请日：2011-09-22
申请人： Young-seung Cho , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
发明人： Young-seung Cho , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
IPC分类号： H01L21/336 , H01L21/76 , H01L21/4763
CPC分类号： H01L29/7827 , H01L27/0207 , H01L27/10873 , H01L27/10885 , H01L29/66666
摘要： A method of fabricating a semiconductor device including a vertical channel transistor. The method may include: forming a plurality of first device isolation layers in a substrate as a pattern of lines having a first depth from an upper surface of a substrate, to define a plurality of active regions, forming a plurality of trenches having a second depth smaller than the first depth, etching portions of the substrate that are under some of the plurality of trenches that are selected at a predetermined interval, to form a plurality of device isolation trenches having a third depth that is greater than the second depth, forming second device isolation layers that include an insulating material, in lower portions of the plurality of device isolation trenches, and forming buried bit lines in lower portions of the plurality of trenches and the plurality of device isolation trenches.
摘要翻译：一种制造包括垂直沟道晶体管的半导体器件的方法。该方法可以包括：在衬底中形成多个第一器件隔离层作为具有从衬底的上表面的第一深度的线的图案，以限定多个有源区，形成具有第二深度的多个沟槽小于第一深度，蚀刻在以预定间隔选择的多个沟槽中的一些下方的衬底的部分，以形成具有大于第二深度的第三深度的多个器件隔离沟槽，形成第二深度在所述多个器件隔离沟槽的下部包括绝缘材料的器件隔离层，以及在所述多个沟槽的下部和所述多个器件隔离沟槽中形成掩埋位线。

28. 发明申请

US20130115745A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION TRENCHES SELF-ALIGNED TO GATE TRENCHES 审中-公开
标题翻译：制造半导体器件的方法，包括自对准门极隔离器件隔离开关
公开(公告)号：US20130115745A1
公开(公告)日：2013-05-09
申请号：US13607315
申请日：2012-09-07
申请人： Hyun-woo Chung , Hyeong-sun Hong , Yoo-sang Hwang , Ji-young Kim , Jay-bok Choi
发明人： Hyun-woo Chung , Hyeong-sun Hong , Yoo-sang Hwang , Ji-young Kim , Jay-bok Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/10876
摘要： Methods of manufacturing a semiconductor device can be provided by forming a structure including a plurality of gate trenches that extend in a first direction and a mold layer having openings and that extend in the first direction on a substrate. Filling layers can be formed to fill the openings and the mold layer can be removed so that the filling layers remain on the substrate. A spacer layer can be formed which fills a space between the filling layers directly adjacent to each other at one side of each of the filling layers and forms a spacer at the sidewall of each of the filling layers at the other side of each of the filling layers. Device isolation trenches can be formed that extend in parallel to the plurality of gate trenches by etching the substrate exposed by the spacer layer.
摘要翻译：制造半导体器件的方法可以通过形成包括在第一方向上延伸的多个栅极沟槽和具有开口并且在基板上沿第一方向延伸的模具层的结构来提供。可以形成填充层以填充开口，并且可以去除模具层，使得填充层保留在基底上。可以形成间隔层，其在每个填充层的一侧填充彼此直接相邻的填充层之间的空间，并且在每个填充层的另一侧的每个填充层的侧壁处形成间隔物层。可以通过蚀刻由间隔层暴露的衬底来形成平行于多个栅极沟槽延伸的器件隔离沟槽。

29. 发明授权

US08394697B2 Methods of forming capacitors for semiconductor memory devices 有权
标题翻译：形成半导体存储器件电容器的方法
公开(公告)号：US08394697B2
公开(公告)日：2013-03-12
申请号：US13010297
申请日：2011-01-20
申请人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
发明人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
摘要翻译：公开了一种半导体存储器件的电容器及其形成方法。衬垫层间绝缘层设置在有源区的半导体衬底上。着陆垫和中央着陆垫分别设置在活动区域的周边部分和中心部分中，以穿透垫层间绝缘层。中央着陆垫的上表面与着陆垫的上表面具有不同的面积。掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。下电极形成在埋地塞上。

30. 发明申请

US20120299090A1 Semiconductor Devices Including Dual Gate Electrode Structures And Related Methods 有权
标题翻译：包括双栅电极结构的半导体器件及相关方法
公开(公告)号：US20120299090A1
公开(公告)日：2012-11-29
申请号：US13298644
申请日：2011-11-17
申请人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
发明人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
IPC分类号： H01L29/78
CPC分类号： G11C11/4096 , G11C11/404 , G11C11/4085 , H01L21/823437 , H01L27/10823 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L29/41741 , H01L29/4236 , H01L29/66484 , H01L29/66613 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.
摘要翻译：半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。此外，第一和第二栅电极可以是电隔离的。还讨论了相关设备，结构，操作方法和制造方法。

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