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1. 发明授权

US08742493B2 Semiconductor devices having vertical channel transistors and methods for fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08742493B2
公开(公告)日：2014-06-03
申请号：US13285263
申请日：2011-10-31
申请人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
发明人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
IPC分类号： H01L27/108
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/1033 , H01L29/1087 , H01L29/66666 , H01L29/7831
摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.
摘要翻译：半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

2. 发明申请

US20120119286A1 SEMICONDUCTOR DEVICES HAVING VERTICAL CHANNEL TRANSISTORS AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有垂直通道晶体管的半导体器件及其制造方法
公开(公告)号：US20120119286A1
公开(公告)日：2012-05-17
申请号：US13285263
申请日：2011-10-31
申请人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
发明人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/1033 , H01L29/1087 , H01L29/66666 , H01L29/7831
摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.
摘要翻译：半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

3. 发明授权

US09601420B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US09601420B2
公开(公告)日：2017-03-21
申请号：US14018709
申请日：2013-09-05
申请人： Yoo-Sang Hwang , Hyun-Woo Chung , Dae-Ik Kim
发明人： Yoo-Sang Hwang , Hyun-Woo Chung , Dae-Ik Kim
IPC分类号： H01L21/768 , H01L23/498 , H01L23/522 , H01L27/108 , H01L23/532 , H01L21/762
CPC分类号： H01L23/49811 , H01L21/76229 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/522 , H01L23/5222 , H01L23/53295 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces.

4. 发明申请

US20100193880A1 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20100193880A1
公开(公告)日：2010-08-05
申请号：US12662150
申请日：2010-04-01
申请人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
发明人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
IPC分类号： H01L23/52 , H01L27/088
CPC分类号： H01L27/10894 , H01L21/82345 , H01L21/823456 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L29/4236 , H01L29/66621
摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.
摘要翻译：半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。外围栅极图案可以设置在半导体衬底的外围有源区上。细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

5. 发明授权

US09570510B2 Magnetoresistive random access memory devices and methods of manufacturing the same 有权
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US09570510B2
公开(公告)日：2017-02-14
申请号：US14724725
申请日：2015-05-28
申请人： Eun-Jung Kim , Se-Myeong Jang , Dae-Ik Kim , Je-Min Park , Yoo-Sang Hwang
发明人： Eun-Jung Kim , Se-Myeong Jang , Dae-Ik Kim , Je-Min Park , Yoo-Sang Hwang
IPC分类号： H01L29/82 , H01L27/22 , H01L29/78 , H01L43/08
CPC分类号： H01L27/228 , H01L29/7827 , H01L43/08
摘要： An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other. MTJ structures may be electrically connected to corresponding ones of the second semiconductor patterns. Each bit line structure may electrically connect two adjacent MTJ structures in the first direction to each other.
摘要翻译： MRAM器件可以包括布置在衬底上的半导体结构，公共源极区，漏极区，沟道区，栅极结构，字线结构，MTJ结构和位线结构。每个半导体结构可以包括具有基本上线性形状的第一半导体图案，该第一半导体图案沿着基本上平行于基板的顶表面的第一方向延伸，以及多个第二图案，每个第二图案沿基本上垂直于基板的第三方向延伸衬底的顶表面。可以在每个半导体结构中形成公共源极区域和漏极区域，以在第三方向上彼此间隔开，并且沟道区域可以布置在公共源极区域和漏极区域之间。可以在相邻的第二半导体图案之间沿第二方向形成栅极结构。字线结构可以将布置在第一方向上的栅极结构彼此电连接。 MTJ结构可以电连接到相应的第二半导体图案。每个位线结构可以将第一方向上的两个相邻的MTJ结构彼此电连接。

6. 发明授权

US08120123B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08120123B2
公开(公告)日：2012-02-21
申请号：US12662150
申请日：2010-04-01
申请人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
发明人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
IPC分类号： H01L23/52 , H01L27/088
CPC分类号： H01L27/10894 , H01L21/82345 , H01L21/823456 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L29/4236 , H01L29/66621
摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.
摘要翻译：半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。外围栅极图案可以设置在半导体衬底的外围有源区上。细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

7. 发明授权

US08450786B2 Semiconductor devices including buried gate electrodes 有权
标题翻译：包括掩埋栅电极的半导体器件
公开(公告)号：US08450786B2
公开(公告)日：2013-05-28
申请号：US13241716
申请日：2011-09-23
申请人： Dae-Ik Kim , Yong-Il Kim
发明人： Dae-Ik Kim , Yong-Il Kim
IPC分类号： H01L27/108
CPC分类号： H01L27/088 , H01L21/82345 , H01L21/823456 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.
摘要翻译：提供了能够减小厚度的半导体器件，采用该半导体器件的电子产品及其制造方法。制造半导体器件的方法包括制备具有第一和第二有源区的半导体衬底。第一有源区中的第一晶体管包括第一栅极图案和第一杂质区域。第二晶体管，第二有源区包括第二栅极图案和第二杂质区域。第一导电图案在第一晶体管上，其中第一导电图案的至少一部分设置在与半导体衬底的上表面相同的距离处，作为第二栅极图案的至少一部分。第一导电图案可以形成在第一晶体管上，而形成第二晶体管。

8. 发明授权

US08344517B2 Integrated circuit devices including air spacers separating conductive structures and contact plugs and methods of fabricating the same 有权
标题翻译：集成电路装置包括分隔导电结构和接触插塞的气垫片及其制造方法
公开(公告)号：US08344517B2
公开(公告)日：2013-01-01
申请号：US13469434
申请日：2012-05-11
申请人： Dae-Ik Kim , Je-Min Park , Chang-Suk Hyun
发明人： Dae-Ik Kim , Je-Min Park , Chang-Suk Hyun
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76834 , H01L23/5222 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes first and second conductive structures spaced apart from one another on a substrate along a first direction. The first and second conductive structures extend in a second direction substantially perpendicular to the first direction. A contact plug is interposed between the first and second conductive structures and is separated therefrom along the first direction by respective air gaps on opposite sides of the contact plug. The air gaps define first and second air spacers that electrically insulate the contact plug from the first and second conductive structures, respectively. An upper insulation layer covers the first and second air spacers and the first and second conductive structures. The air spacers may sufficiently reduce the loading capacitance between the conductive structures. Related fabrication methods are also discussed.
摘要翻译：集成电路器件包括沿着第一方向在衬底上彼此间隔开的第一和第二导电结构。第一和第二导电结构在基本上垂直于第一方向的第二方向上延伸。接触塞被插入在第一和第二导电结构之间，并且通过接触插塞的相对侧上的相应气隙沿第一方向与其分离。气隙限定分别使接触塞与第一和第二导电结构电绝缘的第一和第二空气间隔件。上绝缘层覆盖第一和第二空气间隔件以及第一和第二导电结构。空气间隔件可以充分降低导电结构之间的负载电容。还讨论了相关的制造方法。

9. 发明申请

US20090072307A1 Semiconductor integrated circuit and method of manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US20090072307A1
公开(公告)日：2009-03-19
申请号：US12230614
申请日：2008-09-02
申请人： Dae-Ik Kim , Yong-Il Kim
发明人： Dae-Ik Kim , Yong-Il Kim
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/823456 , H01L29/1037 , H01L29/66583 , H01L29/66621
摘要： A semiconductor integrated circuit includes a semiconductor substrate, a plurality of trenches formed to extend in one direction in the semiconductor substrate, at least one connecting trench connecting at least two of the plurality of trenches to each other, a plurality of trench transistors including a plurality of gate electrodes, each gate electrode partially filling a corresponding trench, and a capping layer filling the at least one connecting trench.
摘要翻译：半导体集成电路包括半导体衬底，形成为在半导体衬底中沿一个方向延伸的多个沟槽，至少一个将多个沟槽中的至少两个彼此连接的连接沟槽，多个沟槽晶体管，其包括多个的栅电极，每个栅电极部分地填充相应的沟槽，以及填充所述至少一个连接沟槽的封盖层。

10. 发明申请

US20120217631A1 INTEGRATED CIRCUIT DEVICES INCLUDING AIR SPACERS SEPARATING CONDUCTIVE STRUCTURES AND CONTACT PLUGS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：集成电路装置，包括分隔导电结构和接触片的空气隔离器及其制造方法
公开(公告)号：US20120217631A1
公开(公告)日：2012-08-30
申请号：US13469434
申请日：2012-05-11
申请人： Dae-Ik Kim , Je-Min Park , Chang-Suk Hyun
发明人： Dae-Ik Kim , Je-Min Park , Chang-Suk Hyun
IPC分类号： H01L23/52
CPC分类号： H01L21/7682 , H01L21/76834 , H01L23/5222 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes first and second conductive structures spaced apart from one another on a substrate along a first direction. The first and second conductive structures extend in a second direction substantially perpendicular to the first direction. A contact plug is interposed between the first and second conductive structures and is separated therefrom along the first direction by respective air gaps on opposite sides of the contact plug. The air gaps define first and second air spacers that electrically insulate the contact plug from the first and second conductive structures, respectively. An upper insulation layer covers the first and second air spacers and the first and second conductive structures. The air spacers may sufficiently reduce the loading capacitance between the conductive structures. Related fabrication methods are also discussed.
摘要翻译：集成电路器件包括沿着第一方向在衬底上彼此间隔开的第一和第二导电结构。第一和第二导电结构在基本上垂直于第一方向的第二方向上延伸。接触塞被插入在第一和第二导电结构之间，并且通过接触插塞的相对侧上的相应气隙沿第一方向与其分离。气隙限定分别使接触塞与第一和第二导电结构电绝缘的第一和第二空气间隔件。上绝缘层覆盖第一和第二空气间隔件以及第一和第二导电结构。空气间隔件可以充分降低导电结构之间的负载电容。还讨论了相关的制造方法。

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