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1. 发明申请

US20160027787A1 PADS INCLUDING CURVED SIDES AND RELATED ELECTRONIC DEVICES, STRUCTURES, AND METHODS 审中-公开
标题翻译：包括曲面和相关电子设备，结构和方法
公开(公告)号：US20160027787A1
公开(公告)日：2016-01-28
申请号：US14847324
申请日：2015-09-08
申请人： Je-Min Park , Seok-Hyun Lim , Tae-Yong Song , Hyun-Chul Yoon , Yoo-Sang Hwang , Hyeon-Ok Jung
发明人： Je-Min Park , Seok-Hyun Lim , Tae-Yong Song , Hyun-Chul Yoon , Yoo-Sang Hwang , Hyeon-Ok Jung
IPC分类号： H01L27/108 , H01L21/3213
CPC分类号： H01L27/10855 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76895 , H01L21/76897 , H01L27/1085 , H01L27/10885 , H01L27/10894 , H01L27/10897
摘要： An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.
摘要翻译：电子器件可以包括衬底和衬底上的多个间隔开的衬垫。每个垫可以包括第一，第二，第三和第四侧，第一和第三侧可以是基本上直的相对侧，并且第二和第四侧可以是相对的弯曲的侧面。还讨论了相关方法，设备和结构。

2. 发明授权

US09461051B2 Methods of forming electronic devices having pads using first and second masks 有权
标题翻译：使用第一和第二掩模形成具有垫的电子设备的方法
公开(公告)号：US09461051B2
公开(公告)日：2016-10-04
申请号：US14847324
申请日：2015-09-08
申请人： Je-Min Park , Seok-Hyun Lim , Tae-Yong Song , Hyun-Chul Yoon , Yoo-Sang Hwang , Hyeon-Ok Jung
发明人： Je-Min Park , Seok-Hyun Lim , Tae-Yong Song , Hyun-Chul Yoon , Yoo-Sang Hwang , Hyeon-Ok Jung
IPC分类号： H01L27/108 , H01L21/3213 , H01L21/768 , H01L21/033 , H01L21/311
CPC分类号： H01L27/10855 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76895 , H01L21/76897 , H01L27/1085 , H01L27/10885 , H01L27/10894 , H01L27/10897
摘要： An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.
摘要翻译：电子器件可以包括衬底和衬底上的多个间隔开的衬垫。每个垫可以包括第一，第二，第三和第四侧，第一和第三侧可以是基本上直的相对侧，并且第二和第四侧可以是相对的弯曲的侧面。还讨论了相关方法，设备和结构。

3. 发明申请

US20140374809A1 PADS INCLUDING CURVED SIDES AND RELATED ELECTRONIC DEVICES, STRUCTURES, AND METHODS 审中-公开
标题翻译：包括曲面和相关电子设备，结构和方法
公开(公告)号：US20140374809A1
公开(公告)日：2014-12-25
申请号：US14105581
申请日：2013-12-13
申请人： Je-Min Park , Seok-Hyun Lim , Tae-Yong Song , Hyun-Chul Yoon , Yoo-Sang Hwang , Hyeon-Ok Jung
发明人： Je-Min Park , Seok-Hyun Lim , Tae-Yong Song , Hyun-Chul Yoon , Yoo-Sang Hwang , Hyeon-Ok Jung
IPC分类号： H01L27/108 , H01L23/528
CPC分类号： H01L27/10855 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76895 , H01L21/76897 , H01L27/1085 , H01L27/10885 , H01L27/10894 , H01L27/10897
摘要： An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.
摘要翻译：电子器件可以包括衬底和衬底上的多个间隔开的衬垫。每个垫可以包括第一，第二，第三和第四侧，第一和第三侧可以是基本上直的相对侧，并且第二和第四侧可以是相对的弯曲的侧面。还讨论了相关方法，设备和结构。

4. 发明授权

US08901645B2 Semiconductor devices including bit line contact plug and peripheral transitor 有权
标题翻译：半导体器件包括位线接触插头和外设过渡器
公开(公告)号：US08901645B2
公开(公告)日：2014-12-02
申请号：US13864347
申请日：2013-04-17
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L27/108
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
摘要翻译：具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管和周边晶体管上电极。位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

5. 发明申请

US20130228856A1 SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR 有权
公开(公告)号：US20130228856A1
公开(公告)日：2013-09-05
申请号：US13864347
申请日：2013-04-17
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/78
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

6. 发明授权

US08461687B2 Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same 有权
标题翻译：包括位线接触插头和掩埋沟道阵列晶体管的半导体器件，以及包括其的电子电路板和电子系统的半导体模块
公开(公告)号：US08461687B2
公开(公告)日：2013-06-11
申请号：US13072907
申请日：2011-03-28
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/40 , H01L29/66
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
摘要翻译：具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管和周边晶体管上电极。位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

7. 发明申请

US20110241102A1 SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND BURIED CHANNEL ARRAY TRANSISTOR, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULES, ELECTRONIC CIRCUIT BOARDS AND ELECTRONIC SYSTEMS INCLUDING THE SAME 有权
标题翻译：包括位线接触插头和布线通道阵列晶体管，其制造方法和半导体模块，电子电路板和包括其的电子系统的半导体器件
公开(公告)号：US20110241102A1
公开(公告)日：2011-10-06
申请号：US13072907
申请日：2011-03-28
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/78
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
摘要翻译：具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管和周边晶体管上电极。位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

8. 发明授权

US07510914B2 Semiconductor devices having fuses and methods of forming the same 有权
标题翻译：具有保险丝的半导体器件及其形成方法
公开(公告)号：US07510914B2
公开(公告)日：2009-03-31
申请号：US11447944
申请日：2006-06-07
申请人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
发明人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.
摘要翻译：提供具有多个保险丝的半导体器件及其形成方法。该半导体器件具有包括具有单元区域和/或保险丝盒区域的衬底的熔丝。可以在基板上形成第一绝缘中间层。可以在第一绝缘中间层上形成第一蚀刻停止层。可以在单元区域的第一蚀刻停止层上形成包括阻挡层，金属层和/或覆盖层的金属布线。彼此间隔开的保险丝可以形成在保险丝盒区域的第一蚀刻停止层上。每个熔断器可以包括阻挡层和/或金属层。具有暴露熔丝盒区域的开口的第二绝缘夹层可以形成在金属布线和/或第一蚀刻停止层上。蚀刻停止层可以允许保险丝更均匀地形成并且降低断开保险丝的可能性。

9. 发明授权

US09589964B1 Methods of fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09589964B1
公开(公告)日：2017-03-07
申请号：US14748593
申请日：2015-06-24
申请人： Seokhyun Lim , Hyun-Chul Yoon , Younghan Kim , Jin Il Oh , Soonwon Hwang
发明人： Seokhyun Lim , Hyun-Chul Yoon , Younghan Kim , Jin Il Oh , Soonwon Hwang
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/10814 , H01L27/10894 , H01L28/55 , H01L28/90
摘要： A method of fabricating a semiconductor device with conductive patterns comprises sequentially forming an etch-target layer and a middle mold layer on a substrate, forming a first upper mold pattern and a second upper mold pattern on the middle mold layer to have top surfaces at different levels, etching the middle mold layer using the first and second upper mold patterns as an etch mask to form first and second middle mold patterns, respectively, forming a third middle mold pattern between the first and second middle mold patterns, and etching the etch-target layer using the first to third middle mold patterns as an etch mask to form conductive patterns.
摘要翻译：制造具有导电图案的半导体器件的方法包括在衬底上顺序地形成蚀刻目标层和中间模具层，在中间模具层上形成第一上部模具图案和第二上部模具图案以使顶部表面处于不同的顶部表面使用第一和第二上模具图案蚀刻中间模具层作为蚀刻掩模，分别形成第一和第二中间模具图案，在第一和第二中间模具图案之间形成第三中间模具图案，目标层使用第一至第三中模模型作为蚀刻掩模以形成导电图案。

10. 发明申请

US20160104671A1 SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR 审中-公开
公开(公告)号：US20160104671A1
公开(公告)日：2016-04-14
申请号：US14970160
申请日：2015-12-15
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L23/528 , H01L23/535 , H01L29/06 , H01L27/108 , H01L29/78
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

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