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1. 发明申请

US20120025300A1 Semiconductor Devices Including Vertical Channel Transistors And Methods Of Manufacturing The Same 有权
标题翻译：包括垂直通道晶体管的半导体器件及其制造方法
公开(公告)号：US20120025300A1
公开(公告)日：2012-02-02
申请号：US13185961
申请日：2011-07-19
申请人： Hyun-woo Chung , Hyeong-sun Hong , Yong-chul Oh , Yoo-sang Hwang , Cheol-ho Baek , Kang-uk Kim
发明人： Hyun-woo Chung , Hyeong-sun Hong , Yong-chul Oh , Yoo-sang Hwang , Cheol-ho Baek , Kang-uk Kim
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches.
摘要翻译：一种半导体器件，包括沿第一方向延伸的多个掩埋字线和沿第二方向延伸的多个掩埋位线。多个掩埋字线和多个掩埋位线的上表面比衬底的上表面低。构成第一组有源区域中的多个第一有源区域中的构成一对第一有源区域的两个有源区域之间的距离小于其间具有多个掩埋位线的两个相邻有源区域之间的距离。一种制造半导体器件的方法包括在衬底中形成多个第一沟槽，在多个第一沟槽中形成多个第一导电图案，使得一对第一导电图案设置在多个第一沟槽中的每一个中第一沟槽，在所述多个第一沟槽中形成多个第一掩埋图案以覆盖所述多个第一导电图案，通过在所述多个第一沟槽之间蚀刻所述衬底形成多个第二沟槽，以及形成多个第二掩埋图案在多个第二沟槽中。

2. 发明授权

US08766354B2 Semiconductor devices including vertical channel transistors and methods of manufacturing the same 有权
标题翻译：包括垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08766354B2
公开(公告)日：2014-07-01
申请号：US13185961
申请日：2011-07-19
申请人： Hyun-woo Chung , Hyeong-sun Hong , Yong-chul Oh , Yoo-sang Hwang , Cheol-ho Baek , Kang-uk Kim
发明人： Hyun-woo Chung , Hyeong-sun Hong , Yong-chul Oh , Yoo-sang Hwang , Cheol-ho Baek , Kang-uk Kim
IPC分类号： H01L29/66
CPC分类号： H01L27/10876 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches.
摘要翻译：一种半导体器件，包括沿第一方向延伸的多个掩埋字线和沿第二方向延伸的多个掩埋位线。多个掩埋字线和多个掩埋位线的上表面比衬底的上表面低。构成第一组有源区域中的多个第一有源区域中的构成一对第一有源区域的两个有源区域之间的距离小于其间具有多个掩埋位线的两个相邻有源区域之间的距离。一种制造半导体器件的方法包括在衬底中形成多个第一沟槽，在多个第一沟槽中形成多个第一导电图案，使得一对第一导电图案设置在多个第一沟槽中的每一个中第一沟槽，在所述多个第一沟槽中形成多个第一掩埋图案以覆盖所述多个第一导电图案，通过在所述多个第一沟槽之间蚀刻所述衬底形成多个第二沟槽，以及形成多个第二掩埋图案在多个第二沟槽中。

3. 发明授权

US08604558B2 Semiconductor device having improved reliability 有权
标题翻译：具有提高的可靠性的半导体器件
公开(公告)号：US08604558B2
公开(公告)日：2013-12-10
申请号：US13032041
申请日：2011-02-22
申请人： Cheol-ho Baek , Hyeong-sun Hong , Yoo-sang Hwang
发明人： Cheol-ho Baek , Hyeong-sun Hong , Yoo-sang Hwang
IPC分类号： H01L23/48 , H01L29/78
CPC分类号： H01L27/10894 , H01L21/76895 , H01L27/10855 , H01L27/10876 , H01L29/4236
摘要： A semiconductor includes a plurality of active regions that are separated from each other on a substrate by a device isolation layer and extend in a first direction, the active regions having two opposite ends and a center region; wordlines that are buried in and cross the active regions and extend in a second direction, which is different from the first direction, wherein a wordline that crosses an active region crosses between one of the two opposite ends and the center region of the active region; first contact plugs on the two opposite ends of the active regions, each contact plug overlapping a border between the active region and the device isolation layer; and second contact plugs formed on the first contact plugs.
摘要翻译：半导体包括通过器件隔离层在衬底上彼此分离并沿第一方向延伸的多个有源区，所述有源区具有两个相对端和中心区; 字线，其被埋在并穿过有源区并且在与第一方向不同的第二方向上延伸，其中跨过有源区的字线在有源区的两个相对端之一和中心区之间交叉; 在有源区域的两个相对端上的第一接触插塞，每个接触插塞与有源区域和器件隔离层之间的边界重叠; 和形成在第一接触塞上的第二接触塞。

4. 发明申请

US20110221010A1 SEMICONDUCTOR DEVICE HAVING IMPROVED RELIABILITY 有权
标题翻译：具有改进可靠性的半导体器件
公开(公告)号：US20110221010A1
公开(公告)日：2011-09-15
申请号：US13032041
申请日：2011-02-22
申请人： Cheol-ho Baek , Hyeong-sun Hong , Yoo-sang Hwang
发明人： Cheol-ho Baek , Hyeong-sun Hong , Yoo-sang Hwang
IPC分类号： H01L23/48 , H01L29/78
CPC分类号： H01L27/10894 , H01L21/76895 , H01L27/10855 , H01L27/10876 , H01L29/4236
摘要： A semiconductor includes a plurality of active regions that are separated from each other on a substrate by a device isolation layer and extend in a first direction, the active regions having two opposite ends and a center region; wordlines that are buried in and cross the active regions and extend in a second direction, which is different from the first direction, wherein a wordline that crosses an active region crosses between one of the two opposite ends and the center region of the active region; first contact plugs on the two opposite ends of the active regions, each contact plug overlapping a border between the active region and the device isolation layer; and second contact plugs formed on the first contact plugs.
摘要翻译：半导体包括通过器件隔离层在衬底上彼此分离并沿第一方向延伸的多个有源区，所述有源区具有两个相对端和中心区; 字线，其被埋在并穿过有源区并且在与第一方向不同的第二方向上延伸，其中跨过有源区的字线在有源区的两个相对端之一和中心区之间交叉; 在有源区域的两个相对端上的第一接触插塞，每个接触插塞与有源区域和器件隔离层之间的边界重叠; 和形成在第一接触塞上的第二接触塞。

5. 发明授权

US08362536B2 Semiconductor device having vertical channel transistor and methods of fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08362536B2
公开(公告)日：2013-01-29
申请号：US12904344
申请日：2010-10-14
申请人： Hyung-woo Chung , Yong-chul Oh , Yoo-sang Hwang , Gyo-young Jin , Hyeong-sun Hong , Dae-ik Kim
发明人： Hyung-woo Chung , Yong-chul Oh , Yoo-sang Hwang , Gyo-young Jin , Hyeong-sun Hong , Dae-ik Kim
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10805 , H01L27/0207 , H01L27/10876 , H01L27/10885
摘要： A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.
摘要翻译：半导体存储器件包括从衬底延伸以形成垂直沟道区的第一对柱，所述第一对柱具有彼此相邻的第一柱和第二柱，所述第一柱和第二柱以第一方向，设置在形成在所述第一对柱之间的第一沟槽的底表面上的第一位线，所述第一位线在基本上垂直于所述第一方向的第二方向上延伸;第一接触栅极，设置在第一表面上，所述第一支柱具有第一栅极绝缘层，第二触点栅极，设置在所述第二支柱的第一表面上，第二栅极绝缘层之间具有第二栅极绝缘层，所述第一支柱的第一表面和所述第二支柱的第一表面面向相反方向以及设置在第一接触栅极上的第一字线和设置在第二接触栅极上的第二字线，在fi 第一个方向。

6. 发明授权

US08492832B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08492832B2
公开(公告)日：2013-07-23
申请号：US13571805
申请日：2012-08-10
申请人： Ji-young Kim , Gyo-young Jin , Hyeong-sun Hong , Yoo-sang Hwang , Sung-kwan Choi , Hyun-woo Chung
发明人： Ji-young Kim , Gyo-young Jin , Hyeong-sun Hong , Yoo-sang Hwang , Sung-kwan Choi , Hyun-woo Chung
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , H01L27/10823 , H01L29/4236
摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.
摘要翻译：半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

7. 发明申请

US20130115745A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION TRENCHES SELF-ALIGNED TO GATE TRENCHES 审中-公开
标题翻译：制造半导体器件的方法，包括自对准门极隔离器件隔离开关
公开(公告)号：US20130115745A1
公开(公告)日：2013-05-09
申请号：US13607315
申请日：2012-09-07
申请人： Hyun-woo Chung , Hyeong-sun Hong , Yoo-sang Hwang , Ji-young Kim , Jay-bok Choi
发明人： Hyun-woo Chung , Hyeong-sun Hong , Yoo-sang Hwang , Ji-young Kim , Jay-bok Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/10876
摘要： Methods of manufacturing a semiconductor device can be provided by forming a structure including a plurality of gate trenches that extend in a first direction and a mold layer having openings and that extend in the first direction on a substrate. Filling layers can be formed to fill the openings and the mold layer can be removed so that the filling layers remain on the substrate. A spacer layer can be formed which fills a space between the filling layers directly adjacent to each other at one side of each of the filling layers and forms a spacer at the sidewall of each of the filling layers at the other side of each of the filling layers. Device isolation trenches can be formed that extend in parallel to the plurality of gate trenches by etching the substrate exposed by the spacer layer.
摘要翻译：制造半导体器件的方法可以通过形成包括在第一方向上延伸的多个栅极沟槽和具有开口并且在基板上沿第一方向延伸的模具层的结构来提供。可以形成填充层以填充开口，并且可以去除模具层，使得填充层保留在基底上。可以形成间隔层，其在每个填充层的一侧填充彼此直接相邻的填充层之间的空间，并且在每个填充层的另一侧的每个填充层的侧壁处形成间隔物层。可以通过蚀刻由间隔层暴露的衬底来形成平行于多个栅极沟槽延伸的器件隔离沟槽。

8. 发明申请

US20130037882A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130037882A1
公开(公告)日：2013-02-14
申请号：US13571805
申请日：2012-08-10
申请人： Ji-young Kim , Gyo-young Jin , Hyeong-sun Hong , Yoo-sang Hwang , Sung-kwan Choi , Hyun-woo Chung
发明人： Ji-young Kim , Gyo-young Jin , Hyeong-sun Hong , Yoo-sang Hwang , Sung-kwan Choi , Hyun-woo Chung
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , H01L27/10823 , H01L29/4236
摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.
摘要翻译：半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

9. 发明申请

US20130288472A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING BURIED CHANNEL ARRAY 有权
标题翻译：制作带通道阵列的半导体器件的方法
公开(公告)号：US20130288472A1
公开(公告)日：2013-10-31
申请号：US13761376
申请日：2013-02-07
申请人： Jay-Bok Choi , Yoo-Sang Hwang , Ah-Young Kim , Ye-Ro Lee , Gyo-Young Jin , Hyeong-sun Hong
发明人： Jay-Bok Choi , Yoo-Sang Hwang , Ah-Young Kim , Ye-Ro Lee , Gyo-Young Jin , Hyeong-sun Hong
IPC分类号： H01L29/423
CPC分类号： H01L29/42312 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/4236 , H01L29/66621
摘要： A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.
摘要翻译：制造半导体器件的方法包括在衬底中形成第一和第二平行场区域，所述平行场区域沿第一方向延伸，在形成的第一和第二栅极沟槽中形成第一和第二栅极覆盖层在基板中分别去除栅极覆盖层，使得第一着陆焊盘孔被扩展以部分地覆盖掩埋在衬底中的栅极覆盖层，在第一空间中形成层叠焊盘材料层，并形成位线接触层通过将着陆垫材料层平坦化到覆盖层的顶表面的水平面。

10. 发明授权

US10468103B2 Integrated circuit devices including separate memory cells on separate regions of individual substrate 有权
公开(公告)号：US10468103B2
公开(公告)日：2019-11-05
申请号：US15826031
申请日：2017-11-29
申请人： Sung-woo Kim , Jae-kyu Lee , Ki-seok Suh , Hyeong-sun Hong , Yoo-sang Hwang , Gwan-hyeob Koh
发明人： Sung-woo Kim , Jae-kyu Lee , Ki-seok Suh , Hyeong-sun Hong , Yoo-sang Hwang , Gwan-hyeob Koh
IPC分类号： G11C14/00 , H01L45/00 , H01L29/08 , H01L27/108 , H01L23/528 , H01L29/423 , H01L43/08 , H01L43/02 , H01L43/12 , H01L27/24 , H01L27/22 , H01L27/105 , H01L27/02 , G11C7/10 , G11C11/00
摘要： An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

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