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21. 发明申请

US20100078687A1 Method for Transistor Fabrication with Optimized Performance 有权
标题翻译：具有优化性能的晶体管制造方法
公开(公告)号：US20100078687A1
公开(公告)日：2010-04-01
申请号：US12242078
申请日：2008-09-30
申请人： Da Zhang , Voon-Yew Thean , Christopher V. Baiocco , Jie Chen , Weipeng Li , Young Way Teh , Jin Wallner
发明人： Da Zhang , Voon-Yew Thean , Christopher V. Baiocco , Jie Chen , Weipeng Li , Young Way Teh , Jin Wallner
IPC分类号： H01L21/8238 , H01L29/04
CPC分类号： H01L21/823807 , H01L29/045 , H01L29/517 , H01L29/6653 , H01L29/7843
摘要： A semiconductor process and apparatus includes forming channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).
摘要翻译：一种半导体工艺和设备包括在NMOS沟道区中形成具有增强的空穴迁移率的<100>沟道定向CMOS晶体管（24,34），并且通过在PMOS区上沉积第一拉伸蚀刻停止层（51），减小PMOS区域中的沟道缺陷率蚀刻所述拉伸蚀刻停止层（51）以在所述暴露的栅极侧壁上形成拉伸侧壁间隔物（62），然后在所述NMOS和PMOS栅极上沉积第二富氢压缩或中性蚀刻停止层（72）结构（26,36）和拉伸侧壁间隔物（62）。在其它实施例中，沉积并蚀刻第一富氢蚀刻停止层（81）以在暴露的栅极侧壁上形成侧壁间隔物（92），然后在NMOS和PMOS上沉积第二拉伸蚀刻停止层（94）栅极结构（26,36）和侧壁间隔物（92）。

22. 发明授权

US07659156B2 Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer 有权
标题翻译：通过选择性Ge缩合和高K电介质层选择性调制栅极功能的方法
公开(公告)号：US07659156B2
公开(公告)日：2010-02-09
申请号：US11788216
申请日：2007-04-18
申请人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
发明人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4908 , H01L29/513 , H01L29/517
摘要： A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.
摘要翻译：提供一种半导体器件，其包括半导体层（109），介电层（111），具有与其相关联的第一和第二相应功函数的第一和第二栅电极（129,131）和氧化铪层（113）设置在所述介电层和所述第一和第二栅电极之间。

23. 发明授权

US07521720B2 Semiconductor optical devices having fin structures 失效
标题翻译：具有翅片结构的半导体光学器件
公开(公告)号：US07521720B2
公开(公告)日：2009-04-21
申请号：US11465395
申请日：2006-08-17
申请人： Leo Mathew , Yang Du , Voon-Yew Thean
发明人： Leo Mathew , Yang Du , Voon-Yew Thean
IPC分类号： H01L29/16
CPC分类号： H01S5/0262 , B82Y20/00 , H01L27/14643 , H01L27/14687 , H01L29/66803 , H01L29/785 , H01L31/0384 , H01L31/105 , H01L33/08 , H01L33/18 , H01L33/24 , H01S3/169 , H01S5/0261 , H01S5/0421 , H01S5/0425 , H01S5/2205 , H01S5/304 , Y10S977/95
摘要： A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together. The optical devices may also be integrated with other types of semiconductor devices, such as vertical field-effect transistors.
摘要翻译：半导体光学器件包括绝缘层，形成在绝缘层上的光电区域，形成在绝缘层上并与光电区域的第一侧接触的具有第一导电类型的第一电极和具有第二导电类型的第二电极形成在绝缘层上并与光电区域的第二面接触。光电区域可以包括纳米团簇或多孔硅，使得该器件作为发光器件工作。或者，光电区域可以包括本征半导体材料，使得该器件作为光感测装置工作。半导体光学器件可以被进一步表征为垂直光学器件。在一个实施例中，包括发光和光感测装置的不同类型的光学装置可以集成在一起。光学器件还可以与诸如垂直场效应晶体管的其它类型的半导体器件集成。

24. 发明申请

US20080299724A1 METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR 失效
标题翻译：制造具有嵌入式压力器的半导体器件的方法
公开(公告)号：US20080299724A1
公开(公告)日：2008-12-04
申请号：US11756095
申请日：2007-05-31
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅电极的侧壁上形成绝缘层; 限定与绝缘层相邻的半导体衬底中的源区和漏区; 在所述半导体衬底的源区和漏区中注入掺杂剂以形成掺杂源极和漏极区; 形成邻近所述绝缘层的侧壁间隔物; 在所述源极和漏极区域中的所述半导体衬底中形成凹部，其中所述凹部直接在所述间隔物的下方延伸距离沟道区域预定的距离; 以及在所述凹部中形成应力源材料。该方法允许应力源材料形成得更靠近沟道区，从而改善通道中的载流子迁移率，同时不会降低短沟道效应。

25. 发明申请

US20080023803A1 Method for forming vertical structures in a semiconductor device 有权
标题翻译：在半导体器件中形成垂直结构的方法
公开(公告)号：US20080023803A1
公开(公告)日：2008-01-31
申请号：US11496106
申请日：2006-07-31
申请人： Zhonghai Shi , Voon-Yew Thean , Ted R. White
发明人： Zhonghai Shi , Voon-Yew Thean , Ted R. White
IPC分类号： H01L29/04 , H01L21/84
CPC分类号： H01L29/66795 , H01L29/045 , H01L29/785
摘要： A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer (407) having a crystallographic orientation and a second semiconductor layer (405) having a crystallographic orientation; (b) defining an oxide mask (415) in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.
摘要翻译：提供一种用于制造半导体器件的方法，包括（a）提供包括具有<110>晶体取向的第一半导体层（407）和具有<100>晶体取向的第二半导体层（405）的半导体堆叠; （b）在第一半导体层中限定氧化物掩模（415）; 和（c）利用该氧化物掩模对第二半导体层进行图案化。

26. 发明申请

US20080020515A1 Twisted Dual-Substrate Orientation (DSO) Substrates 有权
标题翻译：扭转双基板取向（DSO）基板
公开(公告)号：US20080020515A1
公开(公告)日：2008-01-24
申请号：US11458902
申请日：2006-07-20
申请人： Ted R. White , Leo Mathew , Bich-Yen Nguyen , Zhonghai Shi , Voon-Yew Thean , Mariam G. Sadaka
发明人： Ted R. White , Leo Mathew , Bich-Yen Nguyen , Zhonghai Shi , Voon-Yew Thean , Mariam G. Sadaka
IPC分类号： H01L21/00
CPC分类号： H01L21/845 , H01L21/76264 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g, 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).
摘要翻译：半导体工艺和装置通过形成第二半导体层（214）提供双或混合衬底，所述第二半导体层通过掩埋绝缘体层与基底第一半导体层隔离并且相对于下面的第一半导体层进行晶体学旋转; 在第二半导体层（214）和掩埋绝缘体层（213）中形成STI区（218）; 在STI区域（218）的第一区域（219）中暴露所述第一半导体层（212）; 从所述暴露的第一半导体层（212）外延生长第一外延半导体层（220）; 以及选择性地蚀刻所述第一外延半导体层（220）和所述第二半导体层（214）以形成来自所述第一外延半导体层（220）的CMOS FinFET沟道区域（例如，223）和平面沟道区域（例如，224）第二半导体层（214）。

27. 发明申请

US20070272952A1 ELECTRONIC DEVICES INCLUDING A SEMICONDUCTOR LAYER 有权
标题翻译：包括半导体层的电子器件
公开(公告)号：US20070272952A1
公开(公告)日：2007-11-29
申请号：US11836844
申请日：2007-08-10
申请人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
发明人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
IPC分类号： H01L29/80
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

28. 发明授权

US07285452B2 Method to selectively form regions having differing properties and structure 有权
标题翻译：选择性地形成具有不同性质和结构的区域的方法
公开(公告)号：US07285452B2
公开(公告)日：2007-10-23
申请号：US11351518
申请日：2006-02-10
申请人： Mariam G. Sadaka , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
发明人： Mariam G. Sadaka , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , Y10S438/973
摘要： A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.
摘要翻译：半导体器件形成为具有不同性质的两个物理上分离的区域，例如不同的表面取向，晶体旋转，应变或组成。在一种形式中，在绝缘层上形成具有第一特性的第一层。第一层被分离成第一和第二物理上分开的区域。在这种物理分离之后，只有第一个区域是非晶化的。供体晶片放置成与第一和第二区域接触。对半导体器件进行退火以修改第一和第二分离区域中的第一个以具有与第一和第二分离区域中的第二个不同的特性。去除施主晶片，并且在第一和第二物理分离区域中的每一个中形成至少一个半导体结构。在另一种形式中，分开的区域是本体衬底和本体衬底内的电隔离区域。

29. 发明申请

US20070108481A1 Electronic devices including a semiconductor layer and a process for forming the same 有权
公开(公告)号：US20070108481A1
公开(公告)日：2007-05-17
申请号：US11273092
申请日：2005-11-14
申请人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
发明人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
IPC分类号： H01L29/76
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

30. 发明授权

US07208424B2 Method of forming a semiconductor device having a metal layer 有权
标题翻译：形成具有金属层的半导体器件的方法
公开(公告)号：US07208424B2
公开(公告)日：2007-04-24
申请号：US10943383
申请日：2004-09-17
申请人： Tab A. Stephens , Brian J. Goolsby , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Tab A. Stephens , Brian J. Goolsby , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/785 , Y10S438/963
摘要： A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
摘要翻译：在金属氧化物之上形成金属层，其中在半导体衬底上形成金属氧化物。确定金属层的预定临界尺寸。执行第一蚀刻以将金属层向下蚀刻到金属氧化物并在金属层的侧壁处形成基脚。用于移除基脚以靶向预定临界尺寸的第二蚀刻，其中第二蚀刻对金属氧化物是选择性的。在一个实施例中，在金属层上形成导电层。可以蚀刻导电层的主体，留下与金属层接触的部分。接下来，可以使用化学选择性地蚀刻与金属层接触的部分。

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