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1. 发明授权

US07208424B2 Method of forming a semiconductor device having a metal layer 有权
标题翻译：形成具有金属层的半导体器件的方法
公开(公告)号：US07208424B2
公开(公告)日：2007-04-24
申请号：US10943383
申请日：2004-09-17
申请人： Tab A. Stephens , Brian J. Goolsby , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Tab A. Stephens , Brian J. Goolsby , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/785 , Y10S438/963
摘要： A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
摘要翻译：在金属氧化物之上形成金属层，其中在半导体衬底上形成金属氧化物。确定金属层的预定临界尺寸。执行第一蚀刻以将金属层向下蚀刻到金属氧化物并在金属层的侧壁处形成基脚。用于移除基脚以靶向预定临界尺寸的第二蚀刻，其中第二蚀刻对金属氧化物是选择性的。在一个实施例中，在金属层上形成导电层。可以蚀刻导电层的主体，留下与金属层接触的部分。接下来，可以使用化学选择性地蚀刻与金属层接触的部分。

2. 发明授权

US07091071B2 Semiconductor fabrication process including recessed source/drain regions in an SOI wafer 有权
标题翻译：半导体制造工艺包括在SOI晶片中的凹陷源极/漏极区域
公开(公告)号：US07091071B2
公开(公告)日：2006-08-15
申请号：US11028811
申请日：2005-01-03
申请人： Voon-Yew Thean , Brian J. Goolsby , Bich-Yen Nguyen , Thien T. Nguyen , Tab A. Stephens
发明人： Voon-Yew Thean , Brian J. Goolsby , Bich-Yen Nguyen , Thien T. Nguyen , Tab A. Stephens
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78639
摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
摘要翻译：在绝缘体上硅（SOI）晶片中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构，其中隔离结构优选地延伸穿过有源层到BOX层的BOX层晶圆。去除有源层的上部以形成晶体管沟道结构。在沟道结构上形成栅极电介质，在栅极电介质上形成栅极结构。执行蚀刻通过栅介质，沟道结构和BOX层的暴露部分，然后从衬底体的暴露部分外延生长源极/漏极结构。隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

3. 发明授权

US07911002B2 Semiconductor device with selectively modulated gate work function 有权
标题翻译：具有选择性调制门功能的半导体器件
公开(公告)号：US07911002B2
公开(公告)日：2011-03-22
申请号：US12641714
申请日：2009-12-18
申请人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
发明人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4908 , H01L29/513 , H01L29/517
摘要： A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.
摘要翻译：提供一种半导体器件，其包括半导体层（109），介电层（111），具有与其相关联的第一和第二相应功函数的第一和第二栅电极（129,131）和氧化铪层（113）设置在所述介电层和所述第一和第二栅电极之间。

4. 发明授权

US07659156B2 Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer 有权
标题翻译：通过选择性Ge缩合和高K电介质层选择性调制栅极功能的方法
公开(公告)号：US07659156B2
公开(公告)日：2010-02-09
申请号：US11788216
申请日：2007-04-18
申请人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
发明人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4908 , H01L29/513 , H01L29/517
摘要： A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.
摘要翻译：提供一种半导体器件，其包括半导体层（109），介电层（111），具有与其相关联的第一和第二相应功函数的第一和第二栅电极（129,131）和氧化铪层（113）设置在所述介电层和所述第一和第二栅电极之间。

5. 发明申请

US20100230756A1 SEMICONDUCTOR DEVICE WITH SELECTIVELY MODULATED GATE WORK FUNCTION 有权
标题翻译：具有选择性调节门功能的半导体器件
公开(公告)号：US20100230756A1
公开(公告)日：2010-09-16
申请号：US12641714
申请日：2009-12-18
申请人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
发明人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
IPC分类号： H01L27/12 , H01L29/49
CPC分类号： H01L21/84 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4908 , H01L29/513 , H01L29/517
摘要： A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.
摘要翻译：提供一种半导体器件，其包括半导体层（109），介电层（111），具有与其相关联的第一和第二相应功函数的第一和第二栅电极（129,131）和氧化铪层（113）设置在所述介电层和所述第一和第二栅电极之间。

6. 发明申请

US20080258219A1 Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer 有权
标题翻译：通过选择性Ge缩合和高K电介质层选择性调制栅极功能的方法
公开(公告)号：US20080258219A1
公开(公告)日：2008-10-23
申请号：US11788216
申请日：2007-04-18
申请人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
发明人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
IPC分类号： H01L21/8238 , H01L27/01
CPC分类号： H01L21/84 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4908 , H01L29/513 , H01L29/517
摘要： A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.
摘要翻译：提供一种半导体器件，其包括半导体层（109），介电层（111），具有与其相关联的第一和第二相应功函数的第一和第二栅电极（129,131）和氧化铪层（113）设置在所述介电层和所述第一和第二栅电极之间。

7. 发明授权

US06831350B1 Semiconductor structure with different lattice constant materials and method for forming the same 有权
标题翻译：具有不同晶格常数材料的半导体结构及其形成方法
公开(公告)号：US06831350B1
公开(公告)日：2004-12-14
申请号：US10677844
申请日：2003-10-02
申请人： Chun-Li Liu , Alexander L. Barr , John M. Grant , Bich-Yen Nguyen , Marius K. Orlowski , Tab A. Stephens , Ted R. White , Shawn G. Thomas
发明人： Chun-Li Liu , Alexander L. Barr , John M. Grant , Bich-Yen Nguyen , Marius K. Orlowski , Tab A. Stephens , Ted R. White , Shawn G. Thomas
IPC分类号： H01L2930
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L29/04 , H01L29/665 , H01L29/7833
摘要： A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also disclosed.
摘要翻译：半导体结构包括具有第一晶格常数的第一松弛半导体材料的衬底。半导体器件层覆盖在衬底上，其中半导体器件层包括具有不同于第一晶格常数的第二晶格常数的第二松弛半导体材料。此外，介电层介于基板和半导体器件层之间，其中介电层包括设置在电介质层内的编程过渡区，用于在第一晶格常数和第二晶格常数之间转变。编程的过渡区域包括多个层，多个层中相邻的层具有不同的晶格常数，其中相邻的层之一具有超过形成缺陷所需的第一临界厚度的第一厚度，而另一层具有第二厚度不超过第二临界厚度。多个层中的每个相邻层形成用于促进过渡区中的缺陷迁移到并终止于编程的过渡区的边缘的界面。还公开了制备该方法的方法。

8. 发明授权

US06951783B2 Confined spacers for double gate transistor semiconductor fabrication process 有权
标题翻译：用于双栅晶体管半导体制造工艺的密封间隔物
公开(公告)号：US06951783B2
公开(公告)日：2005-10-04
申请号：US10695163
申请日：2003-10-28
申请人： Leo Mathew , Rode R. Mora , Bich-Yen Nguyen , Tab A. Stephens , Anne M. Vandooren
发明人： Leo Mathew , Rode R. Mora , Bich-Yen Nguyen , Tab A. Stephens , Anne M. Vandooren
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/84
CPC分类号： H01L29/785 , H01L21/823437 , H01L21/823468 , H01L29/66628 , H01L29/66795 , H01L29/66818
摘要： A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.
摘要翻译：半导体制造工艺包括形成覆盖衬底的硅片。栅极电介质形成在鳍片的主面上。在鳍片的至少两个面上形成栅电极。然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。此后，在主翅片面上形成硅化物。在一个实施例中，栅极电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

9. 发明申请

US20080185654A1 ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR FIN HAVING A PLURALITY OF GATE ELECTRODES AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括具有大量门电极的半导体器件的电子器件和用于形成电子器件的工艺
公开(公告)号：US20080185654A1
公开(公告)日：2008-08-07
申请号：US11670833
申请日：2007-02-02
申请人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
发明人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.
摘要翻译：电子设备可以包括具有与第一壁相邻的第一栅电极和与第二壁相邻的第二栅电极的半导体鳍。在一个实施例中，可以形成覆盖半导体鳍片的导电构件，并且导电构件的一部分可以反应以形成第一和第二栅电极。在另一个实施例中，可以形成图案化掩模层，其包括在栅极电极层上的掩模构件，并且可以去除覆盖在半导体鳍片上的掩蔽构件的部分。在另一个实施例中，第一鳍式晶体管结构可以包括半导体鳍片，第一和第二栅电极以及第一绝缘帽。电子器件还可以包括具有比第一绝缘盖更厚的第二绝缘帽的第二鳍式晶体管结构。

10. 发明授权

US07566623B2 Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device 有权
标题翻译：形成包括具有多个栅电极的半导体鳍片的电子器件的工艺
公开(公告)号：US07566623B2
公开(公告)日：2009-07-28
申请号：US11670833
申请日：2007-02-02
申请人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
发明人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.
摘要翻译：电子设备可以包括具有与第一壁相邻的第一栅电极和与第二壁相邻的第二栅电极的半导体鳍。在一个实施例中，可以形成覆盖半导体鳍片的导电构件，并且导电构件的一部分可以反应以形成第一和第二栅电极。在另一个实施例中，可以形成图案化掩模层，其包括在栅极电极层上的掩模构件，并且可以去除覆盖在半导体鳍片上的掩蔽构件的部分。在另一个实施例中，第一鳍式晶体管结构可以包括半导体鳍片，第一和第二栅电极以及第一绝缘帽。电子器件还可以包括具有比第一绝缘盖更厚的第二绝缘帽的第二鳍式晶体管结构。

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