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21. 发明申请

US20080157182A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080157182A1
公开(公告)日：2008-07-03
申请号：US11980632
申请日：2007-10-31
申请人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
发明人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7881 , H01L29/792 , H01L2029/7858
摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.
摘要翻译：示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。半导体器件包括半导体衬底，半导体柱和接触插塞。半导体衬底包括至少一对使用（或功能）作为活性区的翅片。半导体柱可以插入翅片的部分之间以连接散热片。接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

22. 发明授权

US07145763B2 High-voltage electric double layer capacitor 有权
标题翻译：高压双电层电容器
公开(公告)号：US07145763B2
公开(公告)日：2006-12-05
申请号：US11240373
申请日：2005-10-03
申请人： Yu-Tack Kim , Moon-Bae Lee , Sang-Hyun Lee , Sang-Ick Lee , Chul-Wan Park , Jin-Bae Park , Kwang-Chul Roh , Jin-Hyoung Son , Seung-Hwan Song
发明人： Yu-Tack Kim , Moon-Bae Lee , Sang-Hyun Lee , Sang-Ick Lee , Chul-Wan Park , Jin-Bae Park , Kwang-Chul Roh , Jin-Hyoung Son , Seung-Hwan Song
IPC分类号： H01G9/00 , H01G9/02
CPC分类号： H01G9/155 , H01G9/151 , Y02E60/13
摘要： The present invention relates to a high-voltage electric double layer capacitor (EDLC), and more particularly, to an EDLC in which a surge voltage and an operating voltage are enhanced by improving the structure of a unit cell. The EDLC according to the present invention includes a unit cell having at least three electrodes. According to a preferred embodiment of the present invention, the unit cell has a structure constructed by sequentially laminating a first insulating paper layer with a sheet of insulating paper, a first electrode layer with at least two electrodes, a second insulating paper layer with a sheet of insulating paper, and a second electrode layer with at least one electrode. In accordance with the present invention, the number of electrode-facing surfaces increases, and a surge voltage and an operating voltage increase in proportion to the increased number of the electrode-facing surfaces, resulting in a high energy storage density. Accordingly, the present invention has advantages in that an EDLC with a single cell can be applied to products, an EDLC module can be miniaturized, and there is no need for a protection circuit for maintaining voltage balance on a unit cell basis upon fabrication of the module.
摘要翻译：高电压双层电容器（EDLC）技术领域本发明涉及一种高压双电层电容器（EDLC），更具体地说，涉及一种通过改善晶胞结构来提高浪涌电压和工作电压的EDLC。根据本发明的EDLC包括具有至少三个电极的单元电池。根据本发明的优选实施例，单元电池具有通过依次层叠第一绝缘纸层与绝缘纸片，具有至少两个电极的第一电极层，具有片材的第二绝缘纸层而构成的结构的绝缘纸，以及具有至少一个电极的第二电极层。根据本发明，面向电极的表面的数量增加，并且浪涌电压和工作电压与增加的电极面对表面的数量成比例地增加，导致高的储能密度。因此，本发明的优点在于，具有单个电池的EDLC可以应用于产品，EDLC模块可以被小型化，并且不需要保护电路，用于在制造基于单元的基础上保持基于单元电池的电压平衡模块。

23. 发明申请

US20060221551A1 HIGH-VOLTAGE ELECTRIC DOUBLE LAYER CAPACITOR 有权
标题翻译：高压双电层电容器
公开(公告)号：US20060221551A1
公开(公告)日：2006-10-05
申请号：US11240373
申请日：2005-10-03
申请人： Yu-Tack Kim , Jin-Hyoung Son , Moon-Bae Lee , Sang-Hyun Lee , Kwang-Chul Roh , Seung-Hwan Song , Chul-Wan Park , Sang-Ick Lee , Jin-Bae Park
发明人： Yu-Tack Kim , Jin-Hyoung Son , Moon-Bae Lee , Sang-Hyun Lee , Kwang-Chul Roh , Seung-Hwan Song , Chul-Wan Park , Sang-Ick Lee , Jin-Bae Park
IPC分类号： H01G9/00
CPC分类号： H01G9/155 , H01G9/151 , Y02E60/13
摘要： The present invention relates to a high-voltage electric double layer capacitor (EDLC), and more particularly, to an EDLC in which a surge voltage and an operating voltage are enhanced by improving the structure of a unit cell. The EDLC according to the present invention includes a unit cell having at least three electrodes. According to a preferred embodiment of the present invention, the unit cell has a structure constructed by sequentially laminating a first insulating paper layer with a sheet of insulating paper, a first electrode layer with at least two electrodes, a second insulating paper layer with a sheet of insulating paper, and a second electrode layer with at least one electrode. In accordance with the present invention, the number of electrode-facing surfaces increases, and a surge voltage and an operating voltage increase in proportion to the increased number of the electrode-facing surfaces, resulting in a high energy storage density. Accordingly, the present invention has advantages in that an EDLC with a single cell can be applied to products, an EDLC module can be miniaturized, and there is no need for a protection circuit for maintaining voltage balance on a unit cell basis upon fabrication of the module.
摘要翻译：高电压双层电容器（EDLC）技术领域本发明涉及一种高压双电层电容器（EDLC），更具体地说，涉及一种通过改善晶胞结构来提高浪涌电压和工作电压的EDLC。根据本发明的EDLC包括具有至少三个电极的单元电池。根据本发明的优选实施例，单元电池具有通过依次层叠第一绝缘纸层与绝缘纸片，具有至少两个电极的第一电极层，具有片材的第二绝缘纸层而构成的结构的绝缘纸，以及具有至少一个电极的第二电极层。根据本发明，面向电极的表面的数量增加，并且浪涌电压和工作电压与增加的电极面对表面的数量成比例地增加，导致高的储能密度。因此，本发明的优点在于，具有单个电池的EDLC可以应用于产品，EDLC模块可以被小型化，并且不需要保护电路，用于在制造基于单元的基础上维持基于单元电池的电压平衡模块。

24. 发明授权

US08773922B2 Non-volatile memory device, memory card and system, and method determining read voltage by comparing referenced program data with comparative read data 失效
标题翻译：非易失性存储器件，存储卡和系统，以及通过将参考程序数据与比较读取数据进行比较来确定读取电压的方法
公开(公告)号：US08773922B2
公开(公告)日：2014-07-08
申请号：US12614545
申请日：2009-11-09
申请人： Seung-Hwan Song , Jaehong Kim , Kyoung Lae Cho , Yong June Kim , Jun Jin Kong , Jong Han Kim
发明人： Seung-Hwan Song , Jaehong Kim , Kyoung Lae Cho , Yong June Kim , Jun Jin Kong , Jong Han Kim
IPC分类号： G11C7/06
CPC分类号： G11C16/26 , G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.
摘要翻译：公开了一种非易失性半导体存储器件及确定读取电压的相关方法。非易失性半导体存储器件包括：包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

25. 发明授权

US08339846B2 Flash memory device, programming and reading methods performed in the same 有权
标题翻译： Flash存储器件，编程和读取方法在同一个执行
公开(公告)号：US08339846B2
公开(公告)日：2012-12-25
申请号：US12856698
申请日：2010-08-16
申请人： Hee-seok Eun , Jong-han Kim , Jae-hong Kim , Dong-hyuk Chae , Seung-hwan Song , Han-woong Yoo , Jun-jin Kong , Young-hwan Lee , Kyoung-lae Cho , Yong-june Kim
发明人： Hee-seok Eun , Jong-han Kim , Jae-hong Kim , Dong-hyuk Chae , Seung-hwan Song , Han-woong Yoo , Jun-jin Kong , Young-hwan Lee , Kyoung-lae Cho , Yong-june Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642
摘要： The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.
摘要翻译：闪存器件包括控制逻辑电路和位电平转换逻辑电路。控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位读命令。在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取）位，然后编程或读取其他2N个单元分布。

26. 发明授权

US08316279B2 Method of estimating and correcting errors in memory cells 有权
标题翻译：估计和纠正存储单元错误的方法
公开(公告)号：US08316279B2
公开(公告)日：2012-11-20
申请号：US12607768
申请日：2009-10-28
申请人： Jaehong Kim , Yong June Kim , Seung Hwan Song
发明人： Jaehong Kim , Yong June Kim , Seung Hwan Song
IPC分类号： G11C29/00
CPC分类号： H03M13/1108 , G06F11/1072
摘要： A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.
摘要翻译：至少由纠错码（ECC）解码器和控制器实施的方法估计并校正存储器单元中的错误。该方法包括使用第一种误差估计方法来识别具有错误产生可能性的存储器单元的第一候选组; 使用用于错误估计的第二方法识别具有错误生成可能性的第二候选组存储器单元; 以及校正通常包括在第一和第二候选组中的至少一个单元中的错误。

27. 发明授权

US08279668B2 Apparatus and method of memory programming 有权
标题翻译：存储器编程的装置和方法
公开(公告)号：US08279668B2
公开(公告)日：2012-10-02
申请号：US12801532
申请日：2010-06-14
申请人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Jong Han Kim , Jae Hong Kim , Young Hwan Lee , Heeseok Eun , Seung-Hwan Song
发明人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Jong Han Kim , Jae Hong Kim , Young Hwan Lee , Heeseok Eun , Seung-Hwan Song
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C29/00 , G11C2216/14
摘要： A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store, the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.
摘要翻译：提供了存储器编程设备和/或方法。存储器编程装置可以包括数据存储单元，第一计数单元，索引存储单元和/或编程单元。数据存储单元可以被配置为存储数据页。第一计数单元可以被配置为通过基于数据页计数包括在至少一个参考阈值电压状态中的单元的数量来生成索引信息。索引存储单元可以被配置为存储所生成的索引信息。编程单元可以被配置为将数据页存储在数据存储单元中，并将生成的索引信息存储在索引存储单元中。第一计数单元可以将生成的索引信息发送到编程单元。存储器编程装置可以监视存储器单元中阈值电压的分布状态。

28. 发明授权

US08276046B2 Apparatus for determining number of bits to be stored in memory cell 失效
标题翻译：用于确定要存储在存储单元中的位数的装置
公开(公告)号：US08276046B2
公开(公告)日：2012-09-25
申请号：US12219103
申请日：2008-07-16
申请人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
发明人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
IPC分类号： H03M13/00
CPC分类号： G11C11/56 , G06F11/1012 , G11C29/00
摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.
摘要翻译：示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

29. 发明授权

US08239726B2 Apparatuses and methods for encoding and decoding 有权
标题翻译：用于编码和解码的装置和方法
公开(公告)号：US08239726B2
公开(公告)日：2012-08-07
申请号：US12010025
申请日：2008-01-18
申请人： Jun Jin Kong , Sung Chung Park , Seung-Hwan Song , Jong Han Kim , Young Hwan Lee , Kyoung Lae Cho , Nam Phil Jo , Sung-Jae Byun
发明人： Jun Jin Kong , Sung Chung Park , Seung-Hwan Song , Jong Han Kim , Young Hwan Lee , Kyoung Lae Cho , Nam Phil Jo , Sung-Jae Byun
IPC分类号： H03M13/00
CPC分类号： H03M13/235 , H03M13/6561
摘要： A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n·p-bit code based on at least one of the input information and the delayed information, where n is a rational number.
摘要翻译：码编码装置包括延迟电路和码发生器。延迟电路基于并行接收的p位输入信息产生延迟信息。延迟信息根据时钟生成。代码生成器基于输入信息和延迟信息中的至少一个生成n·p位代码，其中n是有理数。

30. 发明授权

US08112693B2 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US08112693B2
公开(公告)日：2012-02-07
申请号：US11905734
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： G11C29/00
CPC分类号： G06F11/1072
摘要： An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.
摘要翻译：应用于多电平单元（MLC）方法的存储器的错误控制码（ECC）装置可以包括：旁路控制信号发生器，其生成旁路控制信号; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。另外或在替代方案中，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

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