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21. 发明授权

US07932784B1 Frequency and phase locked loop synthesizer 有权
标题翻译：频率和锁相环合成器
公开(公告)号：US07932784B1
公开(公告)日：2011-04-26
申请号：US11854917
申请日：2007-09-13
申请人： Stephen T. Janesch , William J. Farlow , Scott Robert Humphreys
发明人： Stephen T. Janesch , William J. Farlow , Scott Robert Humphreys
IPC分类号： H03L7/06
CPC分类号： H03L7/091 , H03L7/087 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： The present invention is a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. The FPLL synthesizer includes a variable frequency oscillator, which is controlled by FLL circuitry during the FLL operating mode or by PLL circuitry during the PLL operating mode. The FLL circuitry includes frequency division circuitry for reducing the frequency of the output signal, frequency detection circuitry for measuring the frequency error of the frequency reduced output signal, and a loop filter to control the bandwidth of an FLL control loop formed by the FLL circuitry and the variable frequency oscillator.
摘要翻译：本发明是具有锁相环（FLL）操作模式和锁相环（PLL）操作模式的频率锁相环（FPLL）合成器。 FLL操作模式用于FPLL合成器的快速粗调，后跟PLL操作模式，用于微调和稳定来自FPLL合成器的输出信号的频率。 FPLL合成器包括一个可变频率振荡器，在FLL工作模式下由FLL电路控制，或在PLL工作模式下由PLL电路控制。 FLL电路包括用于降低输出信号的频率的分频电路，用于测量频率降低的输出信号的频率误差的频率检测电路以及用于控制由FLL电路形成的FLL控制环的带宽的环路滤波器，以及变频振荡器。

22. 发明授权

US07746178B1 Digital offset phase-locked loop 有权
标题翻译：数字偏移锁相环
公开(公告)号：US07746178B1
公开(公告)日：2010-06-29
申请号：US12341528
申请日：2008-12-22
申请人： Scott Robert Humphreys , Stephen T. Janesch
发明人： Scott Robert Humphreys , Stephen T. Janesch
IPC分类号： H03L7/06 , H03L7/08
CPC分类号： H03L7/085 , H03L7/0991 , H03L7/16 , H03L2207/12
摘要： The present invention relates to a digital offset phase-locked loop (DOPLL), which may have advantages of size, simplicity, performance, design portability, or any combination thereof, compared to analog-based phase-locked loops (PLLs). The DOPLL may include a digital controlled oscillator (DCO), which provides a controllable frequency output signal based on a digital control signal, a radio frequency (RF) mixer circuit, which provides a reduced-frequency feedback signal based on the controllable frequency output signal without reducing loop gain, a time-to-digital converter (TDC), which provides a digital feedback signal that is a time representation of the reduced-frequency feedback signal, and digital PLL circuitry, which provides the digital control signal based on the digital feedback signal and a digital setpoint signal.
摘要翻译：与基于模拟的锁相环（PLL）相比，本发明涉及数字偏移锁相环（DOPLL），其可以具有尺寸，简单性，性能，设计便携性或其任何组合的优点。 DOPLL可以包括数字控制振荡器（DCO），其提供基于数字控制信号的可控频率输出信号，射频（RF）混频器电路，其基于可控频率输出信号提供降频反馈信号在不降低环路增益的情况下，提供作为降低频率反馈信号的时间表示的数字反馈信号的时间 - 数字转换器（TDC）和数字PLL电路，其提供基于数字信号的数字控制信号反馈信号和数字设定点信号。

23. 发明授权

US06891414B1 Digital calibration for capacitor voltage non-linearity 有权
标题翻译：数字校准电容器电压非线性
公开(公告)号：US06891414B1
公开(公告)日：2005-05-10
申请号：US10794861
申请日：2004-03-05
申请人： Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr. , Paul Gerard Martyniuk , Christopher Truong Ngo
发明人： Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr. , Paul Gerard Martyniuk , Christopher Truong Ngo
IPC分类号： H03L7/06 , H03L7/089 , H03L7/093 , H03L7/18
CPC分类号： H03L7/0891 , H03L7/093 , H03L7/18
摘要： The present invention provides a system for adjusting a selectable capacitance of a variable capacitance array to compensate for voltage non-linearity of the variable capacitance array. In general, the system includes the variable capacitance array and a calibration circuit. The calibration circuit operates to determine a voltage across the variable capacitance array and to generate a capacitance selection signal based on the voltage across the variable capacitance array and a known capacitance versus voltage characteristic of the variable capacitance array.
摘要翻译：本发明提供了一种用于调整可变电容阵列的可选择电容以补偿可变电容阵列的电压非线性的系统。通常，该系统包括可变电容阵列和校准电路。校准电路用于确定可变电容阵列上的电压，并且基于可变电容阵列上的电压和可变电容阵列的已知电容对电压特性来产生电容选择信号。

24. 发明授权

US06693468B2 Fractional-N synthesizer with improved noise performance 有权
标题翻译：具有改进噪声性能的分数N合成器
公开(公告)号：US06693468B2
公开(公告)日：2004-02-17
申请号：US09879672
申请日：2001-06-12
申请人： Scott Robert Humphreys , Alex Wayne Hietala
发明人： Scott Robert Humphreys , Alex Wayne Hietala
IPC分类号： H03B2100
CPC分类号： H03L7/1976
摘要： A fractional sequence generator having a plurality of cascaded accumulators whose carry-outs-upon-overflow are provided over a plurality of recombination paths and selective delays to an adder, the pattern of selective delays being modified by the addition of delay elements in all recombination paths except the last to reduce the number of quantization error terms in the transfer function of the sequence generator. Illustrative embodiments may have any number (greater than one) of accumulators and recombination paths, while continuing to exhibit desired simplified frequency response characteristics.
摘要翻译：具有多个级联累加器的分数序列发生器，其多个复合路径上的进位输出和对加法器的选择性延迟提供，通过在所有复合路径中添加延迟元件来修改选择性延迟的模式除了最后一个以减少序列发生器的传递函数中的量化误差项的数量。示例性实施例可以具有任何数量（大于一个）累加器和复合路径，同时继续呈现期望的简化频率响应特性。

25. 发明授权

US06252434B1 Voltage comparator 有权
标题翻译：电压比较器
公开(公告)号：US06252434B1
公开(公告)日：2001-06-26
申请号：US09593378
申请日：2000-06-15
申请人： Manbir Nag , Scott Robert Humphreys
发明人： Manbir Nag , Scott Robert Humphreys
IPC分类号： H03K522
CPC分类号： H03K5/2481 , H03K5/249
摘要： A voltage comparator (10) includes a differential amplifier (12), a switched latch (32), and a switch (26). The voltage comparator (10) receives a first input signal (18) and a second input signal (20), and produces a first output (38) and a second output (40) by comparing the first and second input signals. A reset input (30) disables and enables the voltage comparator (10).
摘要翻译：电压比较器（10）包括差分放大器（12），开关锁存器（32）和开关（26）。电压比较器（10）接收第一输入信号（18）和第二输入信号（20），并通过比较第一和第二输入信号产生第一输出（38）和第二输出（40）。复位输入（30）禁止并使能电压比较器（10）。

26. 发明授权

US5793825A Method and apparatus for extending an operating frequency range of an instantaneous phase-frequency detector 失效
标题翻译：用于延长瞬时相位频率检测器的工作频率范围的方法和装置
公开(公告)号：US5793825A
公开(公告)日：1998-08-11
申请号：US610034
申请日：1996-03-04
申请人： Scott Robert Humphreys , Raymond Louis Barrett, Jr. , Barry W. Herold
发明人： Scott Robert Humphreys , Raymond Louis Barrett, Jr. , Barry W. Herold
IPC分类号： H03L7/093 , H03D3/24 , H03L7/00 , H04L27/14
CPC分类号： H03L7/093
摘要： A method is used by a detector (102) for extending the operating frequency range of a phase lock loop (100). The detector (102) detects a phase-frequency difference between a reference signal (109) and a generated signal (108) of the phase lock loop (100). The detector (102) includes a divider (202) for counting transitions of the generated signal (108) and a logic element (204) and counter (212) for detecting when the frequency of the generated signal (108) is such that the divider (202) operates outside its linear frequency range in relation to a predetermined transition of the reference signal (109). The detector (102) further includes a register (206) for recording a phase value of the divider (202) coincident with the predetermined transition, or a constant phase value (304, 306) when the frequency of the generated signal (108) is operating outside of the linear range of the divider (202).
摘要翻译：检测器（102）使用一种方法来扩展锁相环（100）的工作频率范围。检测器（102）检测参考信号（109）和锁相环（100）的产生信号（108）之间的相位 - 频率差。检测器（102）包括用于对生成的信号（108）和逻辑元件（204）和计数器（212）的转换进行计数的分频器（202），用于检测所产生的信号（108）的频率何时使分频器（202）相对于参考信号（109）的预定转换在其线性频率范围之外操作。检测器（102）还包括一个寄存器（206），用于当所产生的信号（108）的频率为（108）为...时，用于记录与预定转换一致的分频器的相位值或恒定相位值（304,306）操作在分压器（202）的线性范围之外。

27. 发明申请

US20130194540A1 OPHTHALMIC LENS ASSEMBLY HAVING AN INTEGRATED ANTENNA STRUCTURE 有权
标题翻译：具有集成天线结构的眼镜镜组件
公开(公告)号：US20130194540A1
公开(公告)日：2013-08-01
申请号：US13358579
申请日：2012-01-26
申请人： Randall Braxton Pugh , Daniel B. Otts , Frederick A. Flitsch , Adam Toner , Scott Robert Humphreys
发明人： Randall Braxton Pugh , Daniel B. Otts , Frederick A. Flitsch , Adam Toner , Scott Robert Humphreys
IPC分类号： G02C7/02 , A61F2/16 , G02C7/04
CPC分类号： G02C7/049 , A61F2/1624 , A61F2250/0001 , A61F2250/0002 , B29D11/00038 , B29D11/00817 , G02C7/04 , G02C7/083 , H01Q1/22 , H01Q1/2225 , H01Q7/00
摘要： Antennas and antenna systems may be designed and configured for incorporation into mechanical devices, including medical devices, such as ophthalmic devices, including contact lenses. These antennas and antenna systems may be utilized to transmit data from the mechanical device to a receiver, to receive data from a transmitter, and/or to inductively charge an electromechanical cell or the like incorporated into the mechanical device.
摘要翻译：天线和天线系统可以被设计和配置成并入到机械装置中，包括医疗装置，诸如眼科装置，包括隐形眼镜。这些天线和天线系统可用于将数据从机械设备传送到接收机，从发射机接收数据，和/或感应地对组装在机械设备中的机电电池等进行充电。

28. 发明授权

US07474878B1 Closed loop polar modulation system with open loop option at low power levels 有权
标题翻译：闭环极性调制系统，具有低功耗水平的开环选项
公开(公告)号：US07474878B1
公开(公告)日：2009-01-06
申请号：US11070704
申请日：2005-03-02
申请人： Alexander Wayne Hietala , Niels Jorgen Jensen , Scott Robert Humphreys
发明人： Alexander Wayne Hietala , Niels Jorgen Jensen , Scott Robert Humphreys
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H03L7/1974 , H03C3/0925 , H03C3/0933 , H03C3/0966 , H03C3/0975 , H03C3/0983 , H03C5/00 , H03L7/07
摘要： A polar transmitter that is configurable as either a closed loop polar transmitter or an open loop polar transmitter is provided. In general, the polar transmitter is configured as an open loop polar transmitter when operating at an output power level less than a predetermined threshold and as a closed loop polar transmitter when operating at an output power greater than the predetermined threshold.
摘要翻译：提供可配置为闭环极性发射器或开环极性发射器的极性发射器。通常，当以小于预定阈值的输出功率电平操作时，极坐标发射器被配置为开环极性发射器，并且当以大于预定阈值的输出功率操作时，作为闭环极性发射器。

29. 发明授权

US07449960B2 Frequency modulation linearization system for a Fractional-N offset PLL 有权
标题翻译：用于分数N偏移PLL的频率调制线性化系统
公开(公告)号：US07449960B2
公开(公告)日：2008-11-11
申请号：US11415808
申请日：2006-05-02
申请人： Ryan Lee Bunch , Alexander Wayne Hietala , Scott Robert Humphreys
发明人： Ryan Lee Bunch , Alexander Wayne Hietala , Scott Robert Humphreys
IPC分类号： H03L7/085 , H03L7/089 , H03L7/099
CPC分类号： H03L7/1976 , H03C3/0966 , H03L7/23 , H03L2207/12
摘要： A linearization system is provided for a Fractional-N Offset Phase Locked Loop (FN-OPLL) in a frequency or phase modulation system. In general, the linearization system processes a modulation signal to provide a linearized modulation signal to a fractional-N divider in a reference path of the FN-OPLL such that a frequency or phase modulation component at the output of the FN-OPLL is substantially linear with respect to the modulation signal.
摘要翻译：在频率或相位调制系统中为分数N偏移锁相环（FN-OPLL）提供线性化系统。通常，线性化系统处理调制信号以向FN-OPLL的参考路径中的分数N分频器提供线性调制信号，使得FN-OPLL的输出处的频率或相位调制分量基本上是线性的相对于调制信号。

30. 发明授权

US06838951B1 Frequency synthesizer having VCO bias current compensation 有权
标题翻译：具有VCO偏置电流补偿的频率合成器
公开(公告)号：US06838951B1
公开(公告)日：2005-01-04
申请号：US10453095
申请日：2003-06-03
申请人： Ralph Christopher Nieri , Scott Robert Humphreys , Tracy Hall
发明人： Ralph Christopher Nieri , Scott Robert Humphreys , Tracy Hall
IPC分类号： H03L7/00 , H03L7/113 , H03L7/197
CPC分类号： H03L7/1976 , H03L7/113
摘要： The present invention provides circuitry for maintaining the desired phase noise across the tuning range of a frequency synthesizer by compensating the voltage controlled oscillator (VCO) bias current according to various tuning parameters available within the frequency synthesizer, thereby reducing overall current drain and inductor quality factor requirements. In general, the present invention includes a VCO bias circuit capable of controlling the VCO bias current in response to a control signal provided by additional circuitry based on the operating frequency of the frequency synthesizer. Further, the VCO bias current changes in response to changing the operating frequency of the frequency synthesizer.

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