专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20090098469A1 Process for fabrication of alternating phase shift masks 审中-公开
标题翻译：制造交替相移掩模的工艺
公开(公告)号：US20090098469A1
公开(公告)日：2009-04-16
申请号：US11974249
申请日：2007-10-12
申请人： Kishore K. Chakravorty , Sven Henrichs , Yi-Ping Liu , Henry Yun , Brian Irving , Alexander Tritchkov , Karmen Yung
发明人： Kishore K. Chakravorty , Sven Henrichs , Yi-Ping Liu , Henry Yun , Brian Irving , Alexander Tritchkov , Karmen Yung
IPC分类号： G03F1/00 , B44C1/22
CPC分类号： G03F1/30
摘要： Design rules are described for a phase alternating shift mask for minimum chrome width and maximum segment length, where an embodiment employs during a cleaning process of the mask a megasonic power of 50 Watts at 1 MHz, and 30 Watts at 3 MHz. Some embodiments utilize an dry etch Carbon Tetrafluoride and Dioxygen based process. Other embodiments are described and claimed.
摘要翻译：描述了用于最小镀铬宽度和最大段长度的相位交替移位掩模的设计规则，其中实施例在掩模的清洁处理期间采用1MHz的50瓦特和3MHz的30瓦特的兆声波功率。一些实施方案利用干蚀刻碳四氟化物和基于氧的方法。描述和要求保护其他实施例。

22. 发明授权

US07112285B2 Conductive core substrate fabrication 有权
标题翻译：导电芯基板制造
公开(公告)号：US07112285B2
公开(公告)日：2006-09-26
申请号：US10313935
申请日：2002-12-05
申请人： Kishore K. Chakravorty
发明人： Kishore K. Chakravorty
IPC分类号： H01B13/00
CPC分类号： H05K3/445 , H05K2203/0278 , H05K2203/1476 , H05K2203/1572
摘要： Methods are provided for fabricating plated through hole conductive core substrate which eliminate the secondary step of producing a through hole in the dielectric material plugging the core through hole. In one embodiment of the method in accordance with the invention, a two-step lamination process is provided. One side of the conductive core is provided with a dielectric laminate, a portion of which flows into and coats the core through hole wall. Excess dielectric material flows out of the core through hole preventing plugging. Similarly, the other side of the conductive core is provided with a dielectric laminate, a portion of which flows into the core through hole completing the coating of the core through hole wall forming a dielectric liner. The dielectric liner insulates the conductive core through hole wall from a conductive layer deposited onto the dielectric liner forming a plated through hole.
摘要翻译：提供了用于制造电镀通孔导电芯基板的方法，其消除了在堵塞芯通孔的电介质材料中产生通孔的二次步骤。在根据本发明的方法的一个实施方案中，提供了两步层压方法。导电芯的一侧设置有介电层压板，其一部分流入并穿过芯通孔壁。过量的电介质材料通过防漏插孔流出芯。类似地，导电芯的另一侧设置有介电层压板，其一部分流入芯通孔，从而完成形成电介质衬垫的芯通孔壁的涂层。电介质衬垫将导电芯通过孔壁与沉积在形成电镀通孔的电介质衬垫上的导电层绝缘。

23. 发明授权

US06970362B1 Electronic assemblies and systems comprising interposer with embedded capacitors 有权
标题翻译：电子组件和系统，包括嵌入式电容器的插入器
公开(公告)号：US06970362B1
公开(公告)日：2005-11-29
申请号：US09628705
申请日：2000-07-31
申请人： Kishore K. Chakravorty
发明人： Kishore K. Chakravorty
IPC分类号： H01L23/50 , H01L23/64 , H05K1/14 , H05K1/16 , H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： H01L23/50 , H01L23/642 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H05K1/141 , H05K1/162 , H01L2224/05599
摘要： To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.
摘要翻译：为了降低开关噪声，集成电路管芯的电源端子被耦合到嵌入在管芯和衬底之间的插入器中的至少一个电容器的相应端子。在一个实施例中，插入器是将裸片上的功率和信号导体耦合到衬底上相应导体的多层陶瓷结构。电容器由至少一个高电容率层形成，并且在一个实施例中包括与导电层交错的几个高介电常数层。或者，电容器可以包括至少一个嵌入式分立电容器。还描述了电子系统，数据处理系统和各种制造方法。

24. 发明授权

US06963483B2 Self-aligned coaxial via capacitors 失效
标题翻译：自对准同轴电容器
公开(公告)号：US06963483B2
公开(公告)日：2005-11-08
申请号：US10386981
申请日：2003-03-12
申请人： Kishore K. Chakravorty , Thomas S. Dory , C. Michael Garner
发明人： Kishore K. Chakravorty , Thomas S. Dory , C. Michael Garner
IPC分类号： H01G2/06 , H05K1/11 , H05K1/16 , H05K3/40 , H05K3/46 , H01G4/228
CPC分类号： H05K1/162 , H05K3/4069 , H05K3/4602 , H05K2201/09509 , H05K2201/09809 , H05K2203/0315 , Y10T29/43
摘要： The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.
摘要翻译：同轴电容器的各种实施例是自对准的，并且形成在通孔中，包括盲孔，埋入通孔和电镀通孔。同轴电容器适于利用电镀通孔的电镀作为第一电极。形成电介质层以覆盖第一电极，同时留下通孔的一部分未填充。第二电极形成在未被电介质层填充的通孔左侧的部分中。这种同轴电容器适用于去耦和功率衰减应用，以减少信号和功率噪声和/或减少电子设备中的功率过冲和下降。对于这样的应用，通常期望通常以千位数字编号的多个同轴电容器将并联耦合，以便实现期望的电容水平。

25. 发明授权

US06710525B1 Electrode structure and method for forming electrode structure for a flat panel display 失效
公开(公告)号：US06710525B1
公开(公告)日：2004-03-23
申请号：US09421781
申请日：1999-10-19
申请人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
发明人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
IPC分类号： H01J102
CPC分类号： H01J9/148 , H01J29/467
摘要： An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.

26. 发明授权

US06512861B2 Packaging and assembly method for optical coupling 有权
标题翻译：光耦合的封装和组装方法
公开(公告)号：US06512861B2
公开(公告)日：2003-01-28
申请号：US09892921
申请日：2001-06-26
申请人： Kishore K. Chakravorty , Ian A. Young , Joseph F. Ahadian , Johanna Marie Swan
发明人： Kishore K. Chakravorty , Ian A. Young , Joseph F. Ahadian , Johanna Marie Swan
IPC分类号： G02B612
CPC分类号： G02B6/43 , G02B6/42 , G02B6/4206 , G02B6/4212 , G02B6/4214 , G02B6/4231 , H05K1/0274 , H05K3/3436 , H05K2201/10121 , H05K2201/10734
摘要： A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has optical waveguide structures in addition to electrical connections. An optically active device may be flip-bonded directly to an integrated circuit using solder bump technology. The integrated circuit then flip-bonded or wire-bonded to a BGA package. The package has alignment rails or balls and V-grooves to anchor the alignment rails/balls to align the BGA package to the PCB. The BGA package is bonded to the PCB using solder reflow technology.
摘要翻译：允许一个或多个集成电路和印刷电路板（PCB）之间的电和光耦合的封装除了电连接之外还具有光波导结构。光学活性器件可以使用焊料凸点技术直接触发到集成电路。然后将集成电路翻转或引线接合到BGA封装。该包装具有对准轨道或球和V形槽，以锚定对准轨道/球以将BGA封装对准PCB。使用焊锡回流技术将BGA封装结合到PCB。

27. 发明授权

US06477034B1 Interposer substrate with low inductance capacitive paths 有权
标题翻译：具有低电感电容路径的内置基板
公开(公告)号：US06477034B1
公开(公告)日：2002-11-05
申请号：US09970422
申请日：2001-10-03
申请人： Kishore K. Chakravorty , Michael Walk
发明人： Kishore K. Chakravorty , Michael Walk
IPC分类号： H01G4228
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L2224/16 , H01L2224/16227 , H01L2224/16265 , H01L2924/00014 , H01L2924/15153 , H01L2924/15159 , H01L2924/15165 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/19103 , H01L2924/3011 , H05K1/0306 , H05K1/141 , H05K2201/0175 , H05K2201/0179 , H05K2201/09309 , H05K2201/09718 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2224/0401
摘要： A thin film capacitor provides an interposer substrate between an integrated circuit die and an organic substrate. The interposer substrate includes a first conductive layer deposited on a base substrate layer. A portion of the first conductive layer provides a first electrode region serving as a first plate of the capacitor. Portions of a second conductive layer forming a second electrode region serving as a second plate of the capacitor. A dielectric layer is disposed between the first and second conductive layers to provide for capacitive regions between the first electrode region and the second electrode region. The base substrate layer and die may be based on similar semiconductor materials, such as Silicon or Gallium Arsenide, to provide an improved coefficient of thermal expansion match.
摘要翻译：薄膜电容器在集成电路管芯和有机衬底之间提供插入器衬底。插入器基板包括沉积在基底层上的第一导电层。第一导电层的一部分提供用作电容器的第一板的第一电极区域。形成用作电容器的第二板的第二电极区域的第二导电层的部分。电介质层设置在第一和第二导电层之间以提供第一电极区域和第二电极区域之间的电容区域。基底层和管芯可以基于类似的半导体材料，例如硅或砷化镓，以提供改进的热膨胀系数匹配。

28. 发明授权

US06181569B2 Low cost chip size package and method of fabricating the same 失效
标题翻译：低成本芯片尺寸封装及其制造方法
公开(公告)号：US06181569B2
公开(公告)日：2001-01-30
申请号：US09326905
申请日：1999-06-07
申请人： Kishore K. Chakravorty
发明人： Kishore K. Chakravorty
IPC分类号： H05K118
CPC分类号： H01L24/10 , H01L23/3114 , H01L23/49816 , H01L24/13 , H01L24/48 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05171 , H01L2224/05572 , H01L2224/05616 , H01L2224/05644 , H01L2224/06505 , H01L2224/13 , H01L2224/13022 , H01L2224/13116 , H01L2224/13144 , H01L2224/13155 , H01L2224/14505 , H01L2224/16 , H01L2224/48091 , H01L2924/00013 , H01L2924/00014 , H01L2924/00015 , H01L2924/0002 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H05K3/3436 , H05K2201/0379 , H05K2201/10977 , Y02P70/613 , H01L2924/0105 , H01L2224/13099 , H01L2224/29099 , H01L2924/00 , H01L2224/05552 , H01L2224/05599 , H01L2224/85399 , H01L2224/45099 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A first plurality of metal bumps is formed on a semiconductor wafer containing a plurality of chips, each of the first plurality of bumps being in electrical contact with a contact pad on one of the chips. An encapsulant layer is deposited over the first plurality of metal bumps and then polished to expose a top surface on each of the metal bumps. A second plurality of metal bumps is formed on the exposed top surfaces of the first plurality of plurality of bumps, respectively. The wafer is then sawed to separate the individual chips, yielding semiconductor packages which have the same lateral dimensions as the chips. Alternatively, to facilitate the encapsulation process, the wafer can be sawed into rectangular, multi-chip segments before the encapsulant layer is deposited. After the encapsulant layer has been applied and polished and the second plurality of conductive bumps have been formed, the segments are then separated into individual chips. The first plurality of metal bumps can be deposited directly on the contact pads, with or without an underbump metalization layer, or on metal conductive traces over one or more dielectric layers.
摘要翻译：在包含多个芯片的半导体晶片上形成第一多个金属凸块，所述第一多个凸块中的每一个与所述芯片之一上的接触焊盘电接触。在第一多个金属凸块上沉积密封剂层，然后抛光以暴露每个金属凸块上的顶表面。第二多个金属凸块分别形成在第一多个凸块的暴露的顶表面上。然后锯切晶片以分离各个芯片，产生具有与芯片相同的横向尺寸的半导体封装。或者，为了便于封装工艺，可以在沉积密封剂层之前将晶片锯成矩形的多芯片片段。在施加和抛光密封剂层并形成第二多个导电凸块之后，将这些段分离成单独的芯片。第一多个金属凸块可以直接沉积在具有或不具有底部凹凸金属化层的接触焊盘上，或者在一个或多个电介质层上的金属导电迹线上。

29. 发明授权

US6149792A Row electrode anodization 失效
标题翻译：行电极阳极氧化
公开(公告)号：US6149792A
公开(公告)日：2000-11-21
申请号：US940706
申请日：1997-09-30
申请人： Kishore K. Chakravorty
发明人： Kishore K. Chakravorty
IPC分类号： H01J9/02 , H01J3/02 , H01J9/14 , H01J29/04 , H01J29/46 , H01J31/12 , C25D5/02 , H01L21/288 , H01L21/445
CPC分类号： H01J9/148 , H01J29/467 , H01J3/022
摘要： A structure and method for forming an anodized row electrode for a field emission display device. In one embodiment, the present invention comprises depositing a resistor layer over portions of a row electrode. Next, an inter-metal dielectric layer is deposited over the row electrode. In the present embodiment, the inter-metal dielectric layer deposited over portions of the resistor layer and over pad areas of the row electrode. After the deposition of the inter-metal dielectric layer, the row electrode is subjected to an anodization process such that exposed regions of the row electrode are anodized. In so doing, the present invention provides a row electrode structure which is resistant to row to column electrode shorts and which is protected from subsequent processing steps.
摘要翻译：一种用于形成用于场致发射显示装置的阳极化行电极的结构和方法。在一个实施例中，本发明包括在行电极的部分上沉积电阻层。接下来，在行电极上沉积金属间介电层。在本实施例中，金属间电介质层沉积在电极层的一部分上，并且在行电极的焊盘区域上。在沉积金属间电介质层之后，对行电极进行阳极氧化处理，使得行电极的暴露区域被阳极氧化。这样做，本发明提供了一种对行至列电极短路有抵抗作用的行电极结构，不受后续处理步骤的影响。

30. 发明授权

US5168542A Low loss channel waveguide and method for making the same 失效
标题翻译：低损耗通道波导及其制造方法
公开(公告)号：US5168542A
公开(公告)日：1992-12-01
申请号：US773158
申请日：1991-10-09
申请人： Kishore K. Chakravorty , Chung-Ping Chien
发明人： Kishore K. Chakravorty , Chung-Ping Chien
IPC分类号： G02B6/12 , G02B6/134
CPC分类号： G02B6/1342 , G02B2006/12076
摘要： Optical waveguides for use in planar structures, such as dielectric layers in multichip modules exhibit low optical loss. The optical waveguides are provided by methods that involve doping of the dielectric layers. The waveguides can be used to interconnect electronic elements and transmit signals at speeds that are compatible with high speed electronic elements.
摘要翻译：用于平面结构的光波导，例如多芯片模块中的电介质层，表现出低光损耗。光波导由涉及掺杂介电层的方法提供。波导可以用于互连电子元件并以与高速电子元件兼容的速度传输信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式