专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07852340B2 Scalable shader architecture 有权
标题翻译：可扩展着色器架构
公开(公告)号：US07852340B2
公开(公告)日：2010-12-14
申请号：US11957358
申请日：2007-12-14
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
IPC分类号： G06F15/80 , G06T15/50 , G06T15/00
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

22. 发明授权

US07490208B1 Architecture for compact multi-ported register file 有权
标题翻译：体积小巧的多端口寄存器文件
公开(公告)号：US07490208B1
公开(公告)日：2009-02-10
申请号：US10959560
申请日：2004-10-05
申请人： Lordson Yue , John W. Berendsen , Karim M. Abdalla , Rui M. Bastos , Radoslav Danilak
发明人： Lordson Yue , John W. Berendsen , Karim M. Abdalla , Rui M. Bastos , Radoslav Danilak
IPC分类号： G06F13/372 , G06F12/00
CPC分类号： G06F13/372
摘要： Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port for read operations and for write operations. Either a single read or a single write operation is performed for a given clock via the single port. Moreover, the single-port RAM serially performs N read operations and M write operations associated with a data group using a clock phase of (N+M) clock phases generated from a clock. In another embodiment, a semiconductor device includes the architecture for compact multi-ported register file. The semiconductor device comprises a plurality of register files. Each register file comprises a RAM comprising a port for read operations and for write operations. Moreover, each RAM serially performs N read operations and M write operations associated with one of a plurality of data groups using a corresponding clock phase of (N+M) clock phases generated from a clock. Further, the semiconductor device comprises an input staging unit for staging write data of one or more of the write operations. Continuing, the semiconductor device comprises an output staging unit for staging read data of one or more of the read operations. The semiconductor device can be a graphics processing unit (GPU).
摘要翻译：公开了用于紧凑型多端口寄存器堆的架构。在一个实施例中，寄存器文件包括单端口随机存取存储器（RAM）。单端口RAM包括用于读取操作和写入操作的单个端口。通过单个端口对给定的时钟执行单个读取或单个写入操作。此外，单端口RAM使用从时钟产生的（N + M）个时钟相位的时钟相位来串行地执行与数据组相关联的N个读取操作和M个写入操作。在另一个实施例中，半导体器件包括用于紧凑型多端口寄存器堆的结构。半导体器件包括多个寄存器文件。每个寄存器文件包括RAM，其包括用于读操作和写操作的端口。此外，每个RAM使用从时钟生成的（N + M）个时钟相位的相应时钟相位，串行地执行与多个数据组之一相关联的N个读取操作和M个写入操作。此外，半导体器件包括用于对一个或多个写入操作的写入数据进行分级的输入分段单元。继续地，半导体器件包括用于对读取操作中的一个或多个读取数据进行分级的输出分段单元。半导体器件可以是图形处理单元（GPU）。

23. 发明授权

US07385607B2 Scalable shader architecture 有权
标题翻译：可扩展着色器架构
公开(公告)号：US07385607B2
公开(公告)日：2008-06-10
申请号：US10938042
申请日：2004-09-10
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
IPC分类号： G06F15/16 , G06F15/80 , G06T1/20
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

24. 发明授权

US09069609B2 Scheduling and execution of compute tasks 有权
标题翻译：计划任务的计划和执行
公开(公告)号：US09069609B2
公开(公告)日：2015-06-30
申请号：US13353150
申请日：2012-01-18
申请人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
发明人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4881 , G06F9/4806 , G06F9/50 , G06F2209/483
摘要： One embodiment of the present invention sets forth a technique for assigning a compute task to a first processor included in a plurality of processors. The technique involves analyzing each compute task in a plurality of compute tasks to identify one or more compute tasks that are eligible for assignment to the first processor, where each compute task is listed in a first table and is associated with a priority value and an allocation order that indicates relative time at which the compute task was added to the first table. The technique further involves selecting a first task compute from the identified one or more compute tasks based on at least one of the priority value and the allocation order, and assigning the first compute task to the first processor for execution.
摘要翻译：本发明的一个实施例提出了一种用于将计算任务分配给包括在多个处理器中的第一处理器的技术。该技术涉及分析多个计算任务中的每个计算任务以识别符合分配给第一处理器的一个或多个计算任务，其中每个计算任务在第一表中列出并且与优先级值和分配指示将计算任务添加到第一个表的相对时间的顺序。该技术还包括基于优先级值和分配顺序中的至少一个从所识别的一个或多个计算任务中选择第一任务计算，以及将第一计算任务分配给第一处理器以供执行。

25. 发明授权

US08456481B2 Block linear memory ordering of texture data techniques 有权
标题翻译：阻止纹理数据技术的线性存储器排序
公开(公告)号：US08456481B2
公开(公告)日：2013-06-04
申请号：US13422498
申请日：2012-03-16
申请人： Walter E. Donovan , Emmett M. Kilgariff , Karim M. Abdalla , Joel J. McCormack
发明人： Walter E. Donovan , Emmett M. Kilgariff , Karim M. Abdalla , Joel J. McCormack
IPC分类号： G06F12/00
CPC分类号： G06T15/04 , G06T1/60
摘要： A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.
摘要翻译：根据本发明的一个实施例的组织用于存储纹理数据的存储器的方法包括访问纹理映射的mipmap级别的大小。可以基于mipmap级别的大小来确定块维度。存储器空间（例如，计算机可读介质）可以在逻辑上被划分为多个整数个可变维度的块。块的尺寸以料滴为单位进行测量，每个料滴的固定尺寸为字节。纹理映射的mipmap级别可以存储在存储器空间中。所述mipmap级别的纹理坐标可以通过确定纹理坐标所驻留的料滴的料滴地址并确定特定料滴中的字节地址来转换为存储器空间的字节地址。

26. 发明授权

US08223150B2 Translation of register-combiner state into shader microcode 有权
标题翻译：寄存器组合器状态转换为着色器微码
公开(公告)号：US08223150B2
公开(公告)日：2012-07-17
申请号：US13193524
申请日：2011-07-28
申请人： Brian Cabral , Amy J. Migdal , Rui M. Bastos , Karim M. Abdalla
发明人： Brian Cabral , Amy J. Migdal , Rui M. Bastos , Karim M. Abdalla
IPC分类号： G06T15/50 , G06F12/02 , G06F9/44 , G09G5/36
CPC分类号： G06T15/50 , G06F8/441 , G06T15/005 , G06T2210/32
摘要： An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.
摘要翻译：一种用于将固定功能状态转换为着色器程序的装置和方法。固定功能状态被接收和存储，当检测到新的着色器程序时，固定功能状态被转换为着色器程序指令。由程序指令指定的寄存器被分配给着色器程序中的处理。可以重新映射寄存器以更有效地使用寄存器存储空间。

27. 发明授权

US08004523B1 Translation of register-combiner state into shader microcode 有权
标题翻译：寄存器组合器状态转换为着色器微码
公开(公告)号：US08004523B1
公开(公告)日：2011-08-23
申请号：US11966905
申请日：2007-12-28
申请人： Brian Cabral , Amy J. Migdal , Rui M. Bastos , Karim M. Abdalla
发明人： Brian Cabral , Amy J. Migdal , Rui M. Bastos , Karim M. Abdalla
IPC分类号： G06T15/50 , G06F12/02 , G06F9/44 , G09G5/36
CPC分类号： G06T15/50 , G06F8/441 , G06T15/005 , G06T2210/32
摘要： An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.
摘要翻译：一种用于将固定功能状态转换为着色器程序的装置和方法。固定功能状态被接收和存储，当检测到新的着色器程序时，固定功能状态被转换成着色器程序指令。由程序指令指定的寄存器被分配给着色器程序中的处理。可以重新映射寄存器以更有效地使用寄存器存储空间。

28. 发明申请

US20110169850A1 BLOCK LINEAR MEMORY ORDERING OF TEXTURE DATA 有权
标题翻译：块状数据的线性记忆命令
公开(公告)号：US20110169850A1
公开(公告)日：2011-07-14
申请号：US13073020
申请日：2011-03-28
申请人： Walter E. Donovan , Emmett M. Kilgariff , Karim M. Abdalla , Joel J. McCormack
发明人： Walter E. Donovan , Emmett M. Kilgariff , Karim M. Abdalla , Joel J. McCormack
IPC分类号： G06T11/40
CPC分类号： G06T15/04 , G06T1/60
摘要： A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.
摘要翻译：根据本发明的一个实施例的组织用于存储纹理数据的存储器的方法包括访问纹理映射的mipmap级别的大小。可以基于mipmap级别的大小来确定块维度。存储器空间（例如，计算机可读介质）可以在逻辑上被划分为多个整数个可变维度的块。块的尺寸以料滴为单位进行测量，每个料滴的固定尺寸为字节。纹理映射的mipmap级别可以存储在存储器空间中。所述mipmap级别的纹理坐标可以通过确定纹理坐标所驻留的料滴的料滴地址并确定特定料滴中的字节地址来转换为存储器空间的字节地址。

29. 发明授权

US07821520B1 Fragment processor having dual mode register file 有权
标题翻译：片段处理器具有双模式寄存器文件
公开(公告)号：US07821520B1
公开(公告)日：2010-10-26
申请号：US11009471
申请日：2004-12-10
申请人： Rui M. Bastos , Karim M. Abdalla , Sean J. Treichler , Emmett M. Kilgariff
发明人： Rui M. Bastos , Karim M. Abdalla , Sean J. Treichler , Emmett M. Kilgariff
IPC分类号： G09G5/36 , G06T1/20 , G06F15/16
CPC分类号： G06T1/20
摘要： A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader processor and as a First-In First-Out (FIFO) buffer for a subsequent module. Some embodiments include automatic, programmable hardware conversion between numeric formats, for example, between floating point data and fixed point data.
摘要翻译：一种新的，有用的和不可见的着色器处理器架构，其具有着色器寄存器文件，其既用作内部存储寄存器文件，用于在着色器处理器内临时存储数据，并作为先进先出（FIFO）缓冲器，用于后续模块。一些实施例包括数字格式之间的自动，可编程硬件转换，例如在浮点数据和固定点数据之间。

30. 发明授权

US07797561B1 Automatic functional block level clock-gating 有权
标题翻译：自动功能块级时钟门控
公开(公告)号：US07797561B1
公开(公告)日：2010-09-14
申请号：US11614221
申请日：2006-12-21
申请人： Karim M. Abdalla , Robert J. Hasslen, III
发明人： Karim M. Abdalla , Robert J. Hasslen, III
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： An embodiment of the invention includes receiving an indicator of an activity-level of a functional block within an electronic chip. The functional block is included in a processing pipeline having a plurality of functional blocks. Each functional block from the plurality is configured to receive a clock signal from a clock signal generator. A status of the functional block is determined based on the activity-level. The clock signal to at least a portion of the functional block is disabled when the status is an inactive status.
摘要翻译：本发明的实施例包括接收电子芯片内的功能块的活动级别的指示符。功能块包括在具有多个功能块的处理管线中。来自多个的每个功能块被配置为从时钟信号发生器接收时钟信号。基于活动级别确定功能块的状态。当状态为非活动状态时，到功能块的至少一部分的时钟信号被禁用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式