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21. 发明申请

US20170365612A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20170365612A1
公开(公告)日：2017-12-21
申请号：US15692606
申请日：2017-08-31
申请人： Jang-Gn YUN , Zhiliang XIA , Ahn-Sik Moon , Se-Jun PARK , Joon-Sung LIM , Sung-Min HWANG
发明人： Jang-Gn YUN , Zhiliang XIA , Ahn-Sik Moon , Se-Jun PARK , Joon-Sung LIM , Sung-Min HWANG
IPC分类号： H01L27/1157 , H01L27/11565 , H01L23/528 , H01L27/11582 , H01L23/522
CPC分类号： H01L27/1157 , H01L23/5226 , H01L23/528 , H01L27/11565 , H01L27/11582
摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

22. 发明申请

US20170323901A1 Semiconductor Devices and Methods for Forming the Same 审中-公开
公开(公告)号：US20170323901A1
公开(公告)日：2017-11-09
申请号：US15661718
申请日：2017-07-27
申请人： Jang-Gn Yun , Sunghoi HUR , Jaesun YUN , Joon-Sung LIM
发明人： Jang-Gn Yun , Sunghoi HUR , Jaesun YUN , Joon-Sung LIM
IPC分类号： H01L27/11582 , H01L27/11575 , H01L27/11573
CPC分类号： H01L27/11582 , H01L27/11573 , H01L27/11575
摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

23. 发明申请

US20170040335A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20170040335A1
公开(公告)日：2017-02-09
申请号：US15168349
申请日：2016-05-31
申请人： Joon Sung LIM , Kyu Baik CHANG , Sung Hoi HUR , Woo Jung KIM
发明人： Joon Sung LIM , Kyu Baik CHANG , Sung Hoi HUR , Woo Jung KIM
IPC分类号： H01L27/115
CPC分类号： H01L27/11575 , H01L21/823481 , H01L21/823878 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00
摘要： A semiconductor device includes a substrate, a plurality of memory cell arrays, and an air gap structure. The substrate includes a cell region, a peripheral circuit region, and a boundary region. The boundary region is between the cell region and the peripheral circuit region. The plurality of memory cell arrays are on the cell region. The air gap structure includes a trench formed in the boundary region of the substrate. The air gap structure defines an air gap.
摘要翻译：半导体器件包括衬底，多个存储单元阵列和气隙结构。基板包括单元区域，外围电路区域和边界区域。边界区域在单元区域和外围电路区域之间。多个存储单元阵列位于单元区域上。气隙结构包括形成在基板的边界区域中的沟槽。气隙结构限定气隙。

24. 发明授权

US09548316B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09548316B2
公开(公告)日：2017-01-17
申请号：US14959209
申请日：2015-12-04
申请人： Joon-Sung Lim , Jang-Gn Yun , Sunghoon Bae , Jaesun Yun , Kyu-Baik Chang
发明人： Joon-Sung Lim , Jang-Gn Yun , Sunghoon Bae , Jaesun Yun , Kyu-Baik Chang
IPC分类号： H01L27/12 , H01L27/115 , H01L27/06
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573 , H01L27/11575
摘要： A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.
摘要翻译：半导体器件包括逻辑结构，该逻辑结构包括布置在电路区域中的逻辑电路和覆盖逻辑电路的下绝缘体，逻辑结构上的存储器结构，插入逻辑结构和电路区域中的存储器结构之间的应力松弛结构以及连接结构，其沿着沿着电路区域旁边的器件的连接区域延伸的导电路径将存储器结构与逻辑电路电连接。

25. 发明申请

US20160225714A1 SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20160225714A1
公开(公告)日：2016-08-04
申请号：US14974567
申请日：2015-12-18
申请人： Jang-Gn YUN , Sunghoi HUR , Jaesun YUN , Joon-Sung LIM
发明人： Jang-Gn YUN , Sunghoi HUR , Jaesun YUN , Joon-Sung LIM
IPC分类号： H01L23/528 , H01L27/115 , H01L23/522
CPC分类号： H01L27/11582 , H01L27/11573 , H01L27/11575
摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.
摘要翻译：半导体器件可以包括延伸到台阶区域的单元阵列区域中的单元栅极导电图案，延伸穿过单元栅极导电图案的单元阵列区域中的单元垂直结构，单元栅极导电上的单元栅极接触结构在步进区域中的图案，单元栅极导电图案中的单元栅极接触区域并与单元栅极接触结构对准，与单元栅极导电图案间隔开的第一外围接触结构，与第一外部接触结构间隔开的第二外部接触结构周边接触结构，第一周边接触结构下面的第一周边接触区域和第二周边接触结构下面的第二周边接触区域。单元栅极接触区域可以包括第一元件，并且单元栅极导电图案的其余部分可以基本上不包括第一元件。

26. 发明授权

US08653580B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08653580B2
公开(公告)日：2014-02-18
申请号：US13617044
申请日：2012-09-14
申请人： Joon-Sung Lim , Jongho Park , Okcheon Hong , Jung-Hwan Park
发明人： Joon-Sung Lim , Jongho Park , Okcheon Hong , Jung-Hwan Park
IPC分类号： H01L21/8247
CPC分类号： H01L27/11529 , H01L27/11526 , H01L27/11573 , H01L28/20
摘要： Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a pattern on a substrate. The semiconductor devices may also include a capping dielectric layer on the pattern. The semiconductor devices may further include a first nitride layer on the capping dielectric layer. Moreover, the semiconductor devices may include a second nitride layer on the first nitride layer. A concentration of nitrogen in the first nitride layer may be greater than that in the second nitride layer.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件可以在衬底上包括图案。半导体器件还可以在图案上包括覆盖电介质层。半导体器件还可以包括在覆盖电介质层上的第一氮化物层。此外，半导体器件可以包括在第一氮化物层上的第二氮化物层。第一氮化物层中的氮浓度可以大于第二氮化物层中的浓度。

27. 发明申请

US20110303962A1 NON-VOLATILE MEMORY DEVICES WITH NON-UNIFORM FLOATING GATE COUPLING 有权
标题翻译：具有非均匀浮动门耦合的非易失性存储器件
公开(公告)号：US20110303962A1
公开(公告)日：2011-12-15
申请号：US13158990
申请日：2011-06-13
申请人： Joon-Sung Lim , Jong-Ho Park , Ok-Cheon Hong , Ji-Hwan Jeon
发明人： Joon-Sung Lim , Jong-Ho Park , Ok-Cheon Hong , Ji-Hwan Jeon
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/11519
摘要： A memory device includes a substrate having an active region defined therein that extends linearly along a first direction. The device also includes a select line on the substrate and extending along a second direction to perpendicularly cross the active region, first and second floating gate patterns on the active region and spaced apart along the first direction, and first and second dielectric patterns on respective ones of the first and second floating gate patterns. The device further includes first and second word lines on respective ones of the first and second dielectric patterns and extending in parallel with the select line along the first direction. A first area of overlap of the first word line with the first floating gate pattern and the first dielectric pattern is less than a second area of overlap of the second word line with the second floating gate pattern and the second dielectric pattern. The first word line may be disposed between the select line and the second word line.
摘要翻译：存储器件包括其中限定在其中的有源区域沿着第一方向线性延伸的衬底。该器件还包括在衬底上的选择线，并沿着第二方向延伸以垂直地穿过有源区，有源区上的第一和第二浮动栅极图案并沿着第一方向间隔开，并且在相应的一个上分开的第一和第二电介质图案的第一和第二浮栅图案。该装置还包括在第一和第二电介质图案的相应的第一和第二字线上并沿着第一方向与选择线平行延伸的第一和第二字线。第一字线与第一浮栅图案和第一介电图案的重叠的第一区域小于第二字线与第二浮栅图案和第二介质图案的第二重叠区域。第一字线可以设置在选择线和第二字线之间。

28. 发明授权

US07671400B2 Semiconductor memory device including double spacers on sidewall of flating gate, electronic device including the same 有权
标题翻译：半导体存储器件包括在隔离栅侧壁上的双重间隔物，包括该隔离栅的电子器件
公开(公告)号：US07671400B2
公开(公告)日：2010-03-02
申请号：US12133587
申请日：2008-06-05
申请人： Joon-Sung Lim , Jong-Ho Park , Hyun-Chul Back , Sung-Hun Lee
发明人： Joon-Sung Lim , Jong-Ho Park , Hyun-Chul Back , Sung-Hun Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.
摘要翻译：半导体存储器件包括形成在半导体衬底中以限定多个有源区的器件隔离层。浮动门设置在活动区域上。控制栅极线与浮动栅极的顶表面重叠，并在有源区域上交叉。控制栅极线具有设置在相邻浮动栅极之间的间隙中的延伸部分和相邻浮动栅极的重叠侧壁之间。第一间隔件设置在相邻浮动门的侧壁上。每个第一间隔件沿着有源区的侧壁并且沿着器件隔离层的侧壁延伸。第二间隔件设置在第一间隔件的外侧壁和延伸部分之间，并且设置在装置隔离层的上方。还公开了一种包括半导体存储器件和制造半导体存储器件的方法的电子器件。

29. 发明授权

US09728549B2 Semiconductor devices and methods for forming the same 有权
公开(公告)号：US09728549B2
公开(公告)日：2017-08-08
申请号：US14974567
申请日：2015-12-18
申请人： Jang-Gn Yun , Sunghoi Hur , Jaesun Yun , Joon-Sung Lim
发明人： Jang-Gn Yun , Sunghoi Hur , Jaesun Yun , Joon-Sung Lim
IPC分类号： H01L27/11582 , H01L27/11573 , H01L27/11575
CPC分类号： H01L27/11582 , H01L27/11573 , H01L27/11575
摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

30. 发明授权

US09646983B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US09646983B2
公开(公告)日：2017-05-09
申请号：US14963739
申请日：2015-12-09
申请人： Jang-gn Yun , Joon Sung Lim , Jae-ho Ahn
发明人： Jang-gn Yun , Joon Sung Lim , Jae-ho Ahn
IPC分类号： H01L21/70 , H01L27/11565 , H01L21/033 , H01L29/06 , H01L27/11519 , H01L21/308 , H01L27/11524 , H01L27/1157
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/3086 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/0653
摘要： A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer. A plurality of first spacers covering both side walls of each of the plurality of reference patterns are formed. A plurality of second spacers covering both side walls of each of the plurality of first spacers are formed by removing the plurality of reference patterns. The feature layer is etched using the plurality of second spacers as an etch mask by removing the plurality of first spacers.

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