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1. 发明申请

US20170365612A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20170365612A1
公开(公告)日：2017-12-21
申请号：US15692606
申请日：2017-08-31
申请人： Jang-Gn YUN , Zhiliang XIA , Ahn-Sik Moon , Se-Jun PARK , Joon-Sung LIM , Sung-Min HWANG
发明人： Jang-Gn YUN , Zhiliang XIA , Ahn-Sik Moon , Se-Jun PARK , Joon-Sung LIM , Sung-Min HWANG
IPC分类号： H01L27/1157 , H01L27/11565 , H01L23/528 , H01L27/11582 , H01L23/522
CPC分类号： H01L27/1157 , H01L23/5226 , H01L23/528 , H01L27/11565 , H01L27/11582
摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

2. 发明申请

US20170133389A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
公开(公告)号：US20170133389A1
公开(公告)日：2017-05-11
申请号：US15217313
申请日：2016-07-22
申请人： Jang-Gn YUN , Zhiliang XIA , Ahn-Sik MOON , Se-Jun PARK , Joon-Sung LIM , Sung-Min HWANG
发明人： Jang-Gn YUN , Zhiliang XIA , Ahn-Sik MOON , Se-Jun PARK , Joon-Sung LIM , Sung-Min HWANG
IPC分类号： H01L27/115 , H01L23/528 , H01L23/522
CPC分类号： H01L27/1157 , H01L23/5226 , H01L23/528 , H01L27/11565 , H01L27/11582
摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

3. 发明申请

US20180247950A1 VERTICAL MEMORY DEVICES 审中-公开
公开(公告)号：US20180247950A1
公开(公告)日：2018-08-30
申请号：US15801551
申请日：2017-11-02
申请人： Su-Ok YUN , Jang-Gn YUN , Joon-Sung LIM , Sung-Min HWANG
发明人： Su-Ok YUN , Jang-Gn YUN , Joon-Sung LIM , Sung-Min HWANG
IPC分类号： H01L27/11556 , H01L27/11582
CPC分类号： H01L27/11556 , H01L27/11568 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A vertical memory device includes a gate structure on a peripheral circuit region of a substrate, the substrate including a cell region and the peripheral circuit region, and the gate structure including a first gate electrode, second, third, and fourth gate electrodes sequentially disposed at a plurality of levels, respectively, on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a first epitaxial layer extending through the second gate electrode on the cell region of the substrate, a channel extending through the third and fourth gate electrodes in the vertical direction on the first epitaxial layer, and a second epitaxial layer on a portion of the peripheral circuit region of the substrate adjacent the gate structure.

4. 发明申请

US20160111165A1 METHODS OF OPERATING A NONVOLATILE MEMORY DEVICE 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US20160111165A1
公开(公告)日：2016-04-21
申请号：US14859637
申请日：2015-09-21
申请人： Sunil SHIM , Joon-sung LIM , Jin-Kyu KANG , Euido KIM , Jang-Gn YUN
发明人： Sunil SHIM , Joon-sung LIM , Jin-Kyu KANG , Euido KIM , Jang-Gn YUN
IPC分类号： G11C16/16 , G11C16/34
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/3445
摘要： An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed.
摘要翻译：提供一种非易失性存储装置的操作方法，其顺序地执行多个擦除循环以擦除多个存储块中的至少一个。所述操作方法包括执行所述多个擦除环中的至少一个; 在执行所述至少一个擦除循环之后对所述至少一个存储器块执行后编程操作; 以及执行所述多个擦除环路的剩余擦除环路。当执行每个剩余擦除循环时，不执行后编程操作。

5. 发明申请

US20160225714A1 SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20160225714A1
公开(公告)日：2016-08-04
申请号：US14974567
申请日：2015-12-18
申请人： Jang-Gn YUN , Sunghoi HUR , Jaesun YUN , Joon-Sung LIM
发明人： Jang-Gn YUN , Sunghoi HUR , Jaesun YUN , Joon-Sung LIM
IPC分类号： H01L23/528 , H01L27/115 , H01L23/522
CPC分类号： H01L27/11582 , H01L27/11573 , H01L27/11575
摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.
摘要翻译：半导体器件可以包括延伸到台阶区域的单元阵列区域中的单元栅极导电图案，延伸穿过单元栅极导电图案的单元阵列区域中的单元垂直结构，单元栅极导电上的单元栅极接触结构在步进区域中的图案，单元栅极导电图案中的单元栅极接触区域并与单元栅极接触结构对准，与单元栅极导电图案间隔开的第一外围接触结构，与第一外部接触结构间隔开的第二外部接触结构周边接触结构，第一周边接触结构下面的第一周边接触区域和第二周边接触结构下面的第二周边接触区域。单元栅极接触区域可以包括第一元件，并且单元栅极导电图案的其余部分可以基本上不包括第一元件。

6. 发明申请

US20160163732A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20160163732A1
公开(公告)日：2016-06-09
申请号：US14962263
申请日：2015-12-08
申请人： Joon-Sung LIM , Jang-Gn YUN , Jaesun YUN
发明人： Joon-Sung LIM , Jang-Gn YUN , Jaesun YUN
IPC分类号： H01L27/115 , H01L23/522 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/528 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.
摘要翻译：提供了制造半导体器件的半导体器件和方法。半导体器件可以包括在半导体衬底上包括开口的半导体图案。外围晶体管和外围互连结构可以设置在半导体衬底和半导体图案之间。外围互连结构可以电连接到外围晶体管。单元栅极导电图案可以设置在半导体图案上。单元垂直结构可以延伸穿过单元栅极导电图案并且可以连接到半导体图案。单元位线接触插头可以设置在单元垂直结构上。位线可以设置在单元位线接触插头上。外围位线接触结构可以设置在位线和外围互连结构之间。外围位线接触结构可延伸穿过半导体的开口。

7. 发明申请

US20130093005A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20130093005A1
公开(公告)日：2013-04-18
申请号：US13652998
申请日：2012-10-16
申请人： Jang-Gn YUN , Kwang Soo SEOL , Jungdal CHOI
发明人： Jang-Gn YUN , Kwang Soo SEOL , Jungdal CHOI
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L27/1157 , H01L27/11582
摘要： Three-dimensional (3D) semiconductor memory devices are provided. According to the 3D semiconductor memory device, a gate structure includes gate patterns and insulating patterns alternately stacked on a semiconductor substrate. A vertical active pattern penetrates the gate structure. A gate dielectric layer is disposed between a sidewall of the vertical active pattern and each of the gate patterns. A semiconductor pattern is disposed on the gate structure and is connected to the vertical active pattern. A string drain region is formed in a portion of the semiconductor pattern and is spaced apart from the vertical active pattern.
摘要翻译：提供三维（3D）半导体存储器件。根据3D半导体存储器件，栅极结构包括交替层叠在半导体衬底上的栅极图案和绝缘图案。垂直有源图案穿过栅极结构。栅介质层设置在垂直有源图案的侧壁和每个栅极图案之间。半导体图案设置在栅极结构上并连接到垂直有源图案。串联漏极区域形成在半导体图案的一部分中并且与垂直有源图案间隔开。

8. 发明申请

US20130270624A1 GATE STRUCTURE IN NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件中的门结构
公开(公告)号：US20130270624A1
公开(公告)日：2013-10-17
申请号：US13759195
申请日：2013-02-05
申请人： Jang-Gn YUN , Jung-Dal CHOI , Kwang-Soo SEOL
发明人： Jang-Gn YUN , Jung-Dal CHOI , Kwang-Soo SEOL
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/66833 , H01L29/792
摘要： A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.
摘要翻译：非易失性存储器件的栅极结构及其形成方法，其包括隧道氧化物层图案，电荷陷阱层图案，阻挡介电层图案，其最上层包括第一介电常数大于其的介电常数的材料。包括在隧道氧化物层图案中的材料，以及第一和第二导电层图案。栅极结构包括至少覆盖第二导电层图案的侧壁的第一间隔物。栅极结构包括覆盖第一间隔物的侧壁和第一导电层图案的侧壁的第二间隔物，并且包括具有等于或大于第一介电常数的第二介电常数的材料。在包括栅极结构的非易失性存储器件中，由于后部隧道引起的擦除饱和度降低。

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