专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180337193A1 SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20180337193A1
公开(公告)日：2018-11-22
申请号：US16047712
申请日：2018-07-27
申请人： Joon-Sung Lim , Jang-Gn Yun , Jaesun Yun
发明人： Joon-Sung Lim , Jang-Gn Yun , Jaesun Yun
IPC分类号： H01L27/11582 , H01L27/11573 , H01L23/528 , H01L23/522
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/528 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

2. 发明授权

US09887199B2 Semiconductor devices including a peripheral circuit region and first and second memory regions, and related programming methods 有权
公开(公告)号：US09887199B2
公开(公告)日：2018-02-06
申请号：US14670667
申请日：2015-03-27
申请人： Joon-Sung Lim , Jang-Gn Yun , Hoosung Cho
发明人： Joon-Sung Lim , Jang-Gn Yun , Hoosung Cho
IPC分类号： H01L27/088 , H01L27/105 , H01L27/06 , H01L27/11524 , H01L27/11582 , G11C5/02 , G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： H01L27/105 , G11C5/025 , G11C11/56 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , H01L27/0688 , H01L27/11524 , H01L27/11582
摘要： Semiconductor devices are provided. A semiconductor device includes a peripheral circuit region and a first memory region that are side by side on a substrate. Moreover, the semiconductor device includes a second memory region that is on the peripheral circuit region and the first memory region. Related methods of programming semiconductor devices are also provided.

3. 发明授权

US09698154B2 Semiconductor device 有权
公开(公告)号：US09698154B2
公开(公告)日：2017-07-04
申请号：US15168349
申请日：2016-05-31
申请人： Joon Sung Lim , Kyu Baik Chang , Sung Hoi Hur , Woo Jung Kim
发明人： Joon Sung Lim , Kyu Baik Chang , Sung Hoi Hur , Woo Jung Kim
IPC分类号： H01L21/764 , H01L27/115 , H01L27/11575 , H01L27/1157 , H01L27/11573 , H01L21/8238 , H01L21/8234
CPC分类号： H01L27/11575 , H01L21/823481 , H01L21/823878 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00
摘要： A semiconductor device includes a substrate, a plurality of memory cell arrays, and an air gap structure. The substrate includes a cell region, a peripheral circuit region, and a boundary region. The boundary region is between the cell region and the peripheral circuit region. The plurality of memory cell arrays are on the cell region. The air gap structure includes a trench formed in the boundary region of the substrate. The air gap structure defines an air gap.

4. 发明申请

US20160163730A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160163730A1
公开(公告)日：2016-06-09
申请号：US14959209
申请日：2015-12-04
申请人： JOON-SUNG LIM , JANG-GN YUN , SUNGHOON BAE , JAESUN YUN , KYU-BAIK CHANG
发明人： JOON-SUNG LIM , JANG-GN YUN , SUNGHOON BAE , JAESUN YUN , KYU-BAIK CHANG
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573 , H01L27/11575
摘要： A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.
摘要翻译：半导体器件包括逻辑结构，该逻辑结构包括布置在电路区域中的逻辑电路和覆盖逻辑电路的下绝缘体，逻辑结构上的存储器结构，插入逻辑结构和电路区域中的存储器结构之间的应力松弛结构以及连接结构，其沿着沿着电路区域旁边的器件的连接区域延伸的导电路径将存储器结构与逻辑电路电连接。

5. 发明申请

US20160163635A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160163635A1
公开(公告)日：2016-06-09
申请号：US14957113
申请日：2015-12-02
申请人： Jang-Gn Yun , Jaesun Yun , Joon-Sung Lim
发明人： Jang-Gn Yun , Jaesun Yun , Joon-Sung Lim
IPC分类号： H01L23/528 , H01L23/00 , H01L23/552 , H01L27/115
CPC分类号： H01L23/528 , H01L23/3192 , H01L23/552 , H01L27/0688 , H01L27/11573 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.
摘要翻译：半导体器件包括设置在半导体衬底上的单元半导体图案。在半导体衬底上设置半导体虚设图案。半导体虚拟图案与单元半导体图案共面。第一电路设置在半导体衬底和单元半导体图案之间。第一互连结构设置在半导体衬底和单元半导体图案之间。第一虚拟结构设置在半导体衬底和单元半导体图案之间。第一虚拟结构的一部分与第一互连结构的一部分共面。与半导体图案不重叠的第二虚拟结构设置在半导体衬底上。第二虚拟结构的一部分与第一互连结构的一部分共面。在电池半导体图案和半导体衬底之间以及第一电路和第一互连结构之上设置导电屏蔽图案。

6. 发明申请

US20130009213A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130009213A1
公开(公告)日：2013-01-10
申请号：US13617044
申请日：2012-09-14
申请人： Joon-Sung Lim , Jongho Park , Okcheon Hong , Jung-Hwan Park
发明人： Joon-Sung Lim , Jongho Park , Okcheon Hong , Jung-Hwan Park
IPC分类号： H01L27/10
CPC分类号： H01L27/11529 , H01L27/11526 , H01L27/11573 , H01L28/20
摘要： Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a pattern on a substrate. The semiconductor devices may also include a capping dielectric layer on the pattern. The semiconductor devices may further include a first nitride layer on the capping dielectric layer. Moreover, the semiconductor devices may include a second nitride layer on the first nitride layer. A concentration of nitrogen in the first nitride layer may be greater than that in the second nitride layer.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件可以在衬底上包括图案。半导体器件还可以在图案上包括覆盖电介质层。半导体器件还可以包括在覆盖电介质层上的第一氮化物层。此外，半导体器件可以包括在第一氮化物层上的第二氮化物层。第一氮化物层中的氮浓度可以大于第二氮化物层中的浓度。

7. 发明授权

US10249636B2 Vertical memory devices and methods of manufacturing the same 有权
公开(公告)号：US10249636B2
公开(公告)日：2019-04-02
申请号：US15692606
申请日：2017-08-31
申请人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
发明人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
IPC分类号： H01L27/1157 , H01L23/522 , H01L23/528 , H01L27/11582 , H01L27/11565
摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

8. 发明申请

US20170330894A1 SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20170330894A1
公开(公告)日：2017-11-16
申请号：US15662714
申请日：2017-07-28
申请人： Joon-Sung Lim , Jang-Gn Yun , Jaesun Yun
发明人： Joon-Sung Lim , Jang-Gn Yun , Jaesun Yun
IPC分类号： H01L27/11582 , H01L23/522 , H01L23/528 , H01L27/11573
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/528 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

9. 发明授权

US09786676B2 Vertical memory devices and methods of manufacturing the same 有权
公开(公告)号：US09786676B2
公开(公告)日：2017-10-10
申请号：US15217313
申请日：2016-07-22
申请人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
发明人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
IPC分类号： H01L27/115 , H01L27/1157 , H01L27/11582 , H01L23/522 , H01L23/528
CPC分类号： H01L27/1157 , H01L23/5226 , H01L23/528 , H01L27/11565 , H01L27/11582
摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

10. 发明授权

US09679659B2 Methods of operating a nonvolatile memory device 有权
公开(公告)号：US09679659B2
公开(公告)日：2017-06-13
申请号：US14859637
申请日：2015-09-21
申请人： Sunil Shim , Joon-sung Lim , Jin-Kyu Kang , Euido Kim , Jang-Gn Yun
发明人： Sunil Shim , Joon-sung Lim , Jin-Kyu Kang , Euido Kim , Jang-Gn Yun
IPC分类号： G11C16/04 , G11C16/16 , G11C16/34 , G11C11/56
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/3445
摘要： An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式