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    • 25. 发明授权
    • Semiconductor memory device and method of manufacturing the same
    • 半导体存储器件及其制造方法
    • US07265051B2
    • 2007-09-04
    • US11241924
    • 2005-10-04
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • H01L27/108
    • H01L27/10894H01L27/10814H01L27/10852H01L27/10855H01L27/10885H01L27/10888
    • A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.
    • 一种半导体存储器件和制造方法,包括分别将器件的位线和电容器下电极连接到半导体衬底的有源区的位线连接器和下电极连接器。 连接器使用位于衬底上形成的层间电介质层上的线型自对准光致抗蚀剂掩模图案形成,该掩模图案仅暴露与源极区对应的介电层的一部分,并且沿栅极电极 延伸,以提供不对准余量。 位线连接器和下电极连接器分别由一次性掩模处理形成。 同时形成用于单元区域中的位线连接器的接触孔和周边区域中的金属布线插塞的接触孔,从而减轻随后形成金属布线板期间的蚀刻负担。
    • 27. 发明授权
    • Semiconductor memory device and method for manufacturing the same
    • US06600187B2
    • 2003-07-29
    • US09916736
    • 2001-07-26
    • Jeong-Seok Kim
    • Jeong-Seok Kim
    • H01L27108
    • H01L27/10873H01L27/105H01L27/1052H01L27/10894
    • A technology of preventing the threshold voltage of the transistor of a cell region from increasing and the refresh characteristic of the transistor of the cell region from deteriorating, while maintaining the characteristic of the transistor of core circuit/peripheral circuit regions of a semiconductor memory device, is provided. A semiconductor memory device comprises a first transistor comprised of a first gate, a first gate insulating film, a first source region, and a first drain region formed in core circuit/peripheral circuit regions of a semiconductor memory device having a cell region and core circuit/peripheral circuit regions, a planarized interlayer dielectric film which covers the first transistor, and a second transistor formed in the cell region, including a second source region, a second drain region, a second gate having a height corresponding to the height of the interlayer dielectric film, and a second gate insulating film. The first transistor is formed using conventional manufacturing processes, the second transistor is formed by a damascene method, using the interlayer dielectric film as the basis of a reverse gate pattern.
    • 28. 发明授权
    • Semiconductor memory device with a connector for a lower electrode or a bit line
    • 具有用于下电极或位线的连接器的半导体存储器件
    • US06545306B2
    • 2003-04-08
    • US09988679
    • 2001-11-20
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • H01L27108
    • H01L27/10894H01L27/10814H01L27/10852H01L27/10855H01L27/10885H01L27/10888
    • A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.
    • 一种半导体存储器件和制造方法,包括分别将器件的位线和电容器下电极连接到半导体衬底的有源区的位线连接器和下电极连接器。 连接器使用位于衬底上形成的层间电介质层上的线型自对准光致抗蚀剂掩模图案形成,该掩模图案仅暴露与源极区对应的介电层的一部分,并且沿栅极电极 延伸,以提供不对准余量。 位线连接器和下电极连接器分别由一次性掩模处理形成。 同时形成用于单元区域中的位线连接器的接触孔和周边区域中的金属布线插塞的接触孔,从而减轻随后形成金属布线板期间的蚀刻负担。
    • 29. 发明授权
    • Computer for terminating power without the loss of data and a method thereof
    • 用于在不丢失数据的情况下终止电力的计算机及其方法
    • US06314528B1
    • 2001-11-06
    • US09198405
    • 1998-11-24
    • Jeong-Seok Kim
    • Jeong-Seok Kim
    • G06F1100
    • G06F1/26
    • The present invention comprises a power switch, a central processing unit, a memory, a control unit and a power supply unit. The control unit determines whether a booting operation is successfully preformed, when a power switch is turned to the off position, and then, if a booting operation has been successfully performed, outputs a control signal in order to save data and close all active programs and then turn off power. If a booting operation has not been successfully performed, the control unit outputs a control signal in order to instantly turn off power. The power supply unit turns on or off power according to a control signal from the control unit. The present invention pertains to a computer for terminating power without the loss of data and a method thereof which terminates power only after closing all active programs when the computer's power switch is moved to the off position.
    • 本发明包括电源开关,中央处理单元,存储器,控制单元和电源单元。 控制单元确定是否成功执行启动操作,当电源开关转到关闭位置时,如果启动操作成功执行,则输出控制信号以保存数据并关闭所有活动程序, 然后关闭电源。 如果启动操作未成功执行,则控制单元输出控制信号以便立即关闭电源。 电源单元根据控制单元的控制信号接通或关闭电源。 本发明涉及一种用于在不丢失数据的情况下终止电力的计算机及其方法,其在计算机的电源开关移动到关闭位置之后在关闭所有活动程序之后终止电力。