专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06657886B1 Split local and continuous bitline for fast domino read SRAM 有权
标题翻译：分割本地和连续的位线快速多米诺骨牌SRAM
公开(公告)号：US06657886B1
公开(公告)日：2003-12-02
申请号：US10140549
申请日：2002-05-07
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger
IPC分类号： G11C1140
CPC分类号： G11C11/419
摘要： A high performance domino static random access memory (SRAM) is provided. The domino SRAM includes a plurality of local cell groups. Each of the plurality of local cell groups includes a plurality of SRAM cells and a local true bitline coupled to each of the plurality of SRAM cells of each local cell group. A continuous complement bitline is coupled to each of the plurality of local cell groups and is coupled to each of the plurality of SRAM cells of each local cell group. For a write to the SRAM cell complement node, only driving the continuous complement bitline is required. The domino SRAM reduces the number of required wires and required transistors as compared to prior art domino SRAM and thus the area needed and power consumption are reduced for the domino SRAM.
摘要翻译：提供了高性能的多米诺骨牌静态随机存取存储器（SRAM）。多米诺SRAM包括多个本地小区组。多个本地单元组中的每一个包括耦合到每个本地单元组的多个SRAM单元中的每一个的多个SRAM单元和本地真位线。连续的补码位线耦合到多个局部单元组中的每一个，并耦合到每个本地单元组的多个SRAM单元中的每一个。要写入SRAM单元补码节点，只需要驱动连续的补码位线。与现有技术的多米诺骨牌SRAM相比，多米诺骨牌SRAM减少了所需的电线和所需的晶体管数量，因此为多米诺骨牌SRAM降低了所需的面积和功耗。

22. 发明授权

US08331180B2 Active bit line droop for read assist 有权
标题翻译：有源位线下垂以进行读取辅助
公开(公告)号：US08331180B2
公开(公告)日：2012-12-11
申请号：US12894451
申请日：2010-09-30
申请人： Chad Allen Adams , Sharon Huertas Cesky , Elizabeth Lair Gerhard , Jeffrey Milton Scherer
发明人： Chad Allen Adams , Sharon Huertas Cesky , Elizabeth Lair Gerhard , Jeffrey Milton Scherer
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/419
摘要： A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply voltage, then, subsequently are discharged to a reference voltage, lower than the supply voltage, prior to the word line being activated. Because the bit lines are at a voltage lower than the supply voltage when the SRAM cell is activated, the SRAM cell stability is improved.
摘要翻译：静态随机存取存储器（SRAM）包括存储一位数据的SRAM单元。字线访问SRAM单元，其响应地在读取期间驱动位线真（BLT）或位线补码（BLC）为低电平。 BLT和BLC都被预充电到电源电压，然后在字线被激活之前被放电到低于电源电压的参考电压。由于当SRAM单元被激活时位线的电压低于电源电压，所以提高了SRAM单元的稳定性。

23. 发明授权

US08213249B2 Implementing low power data predicting local evaluation for double pumped arrays 有权
标题翻译：实现低功率数据预测双泵阵列的局部评估
公开(公告)号：US08213249B2
公开(公告)日：2012-07-03
申请号：US12788411
申请日：2010-05-27
申请人： Chad Allen Adams , Sharon Huertas Cesky , Elizabeth Lair Gerhard , Jeffrey Milton Scherer
发明人： Chad Allen Adams , Sharon Huertas Cesky , Elizabeth Lair Gerhard , Jeffrey Milton Scherer
IPC分类号： G11C7/00
CPC分类号： G06F17/5045 , G11C7/067 , G11C7/18 , G11C11/413
摘要： A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation circuit accurately predicts the write data for the next cycle. The domino read local evaluation circuit uses static write data set up prior to a write enable signal to determine the value of the data that is being written into the array. When the data being written to the array matches the data last read the local bitlines stay in their previous state. When the data being written is opposite of the data last read then the bit lines are precharged to the precharge value.
摘要翻译：一种用于实现预测双泵浦阵列的局部评估的低功率数据的方法和静态随机存取存储器（SRAM）电路，以及设置有被摄体电路的设计结构。多米诺骨牌读取本地评估电路的新颖变化准确地预测下一个周期的写入数据。多米诺骨牌读取本地评估电路使用写入使能信号之前设置的静态写入数据来确定正在写入阵列的数据的值。当写入数组的数据与上次读取的数据匹配时，本地位线保持在之前的状态。当写入的数据与上次读取的数据相反时，将位线预充电到预充电值。

24. 发明申请

US20120081949A1 Active Bit Line Droop for Read Assist 有权
标题翻译：有源位线下行读辅助
公开(公告)号：US20120081949A1
公开(公告)日：2012-04-05
申请号：US12894451
申请日：2010-09-30
申请人： Chad Allen Adams , Sharon Huertas Cesky , Elizabeth Lair Gerhard , Jeffrey Milton Scherer
发明人： Chad Allen Adams , Sharon Huertas Cesky , Elizabeth Lair Gerhard , Jeffrey Milton Scherer
IPC分类号： G11C11/40 , G06F17/50 , G11C5/14
CPC分类号： G11C7/12 , G11C11/419
摘要： A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply voltage, then, subsequently are discharged to a reference voltage, lower than the supply voltage, prior to the word line being activated. Because the bit lines are at a voltage lower than the supply voltage when the SRAM cell is activated, the SRAM cell stability is improved.
摘要翻译：静态随机存取存储器（SRAM）包括存储一位数据的SRAM单元。字线访问SRAM单元，其响应地在读取期间驱动位线真（BLT）或位线补码（BLC）为低电平。 BLT和BLC都被预充电到电源电压，然后在字线被激活之前被放电到低于电源电压的参考电压。由于当SRAM单元被激活时位线的电压低于电源电压，所以提高了SRAM单元的稳定性。

25. 发明授权

US07835176B2 Implementing enhanced dual mode SRAM performance screen ring oscillator 有权
标题翻译：实现增强型双模SRAM性能屏环振荡器
公开(公告)号：US07835176B2
公开(公告)日：2010-11-16
申请号：US12360230
申请日：2009-01-27
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C7/1045 , G11C8/18 , G11C11/412 , G11C11/413
摘要： A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.
摘要翻译：一种用于实现增强型双模式静态随机存取存储器（SRAM）性能屏幕环形振荡器（PSRO）的方法和电路，以及设置有被摄体电路的设计结构。双模SRAM PSRO包括连接在一起的多个SRAM基块。多个SRAM基块中的每一个包括八晶体管（8T）SRAM单元，局部评估电路和耦合到SRAM单元的逻辑功能。八晶体管（8T）静态随机存取存储器（SRAM）单元是未修改的8T SRAM单元。双模SRAM PSRO包括一种工作模式，其中输出频率由8T SRAM单元的直写性能决定; 和另一种操作模式，其中输出频率由8T SRAM单元的读取性能决定。

26. 发明授权

US07751266B2 High performance read bypass test for SRAM circuits 失效
标题翻译： SRAM电路的高性能读取旁路测试
公开(公告)号：US07751266B2
公开(公告)日：2010-07-06
申请号：US12146777
申请日：2008-06-26
申请人： Chad Allen Adams , Derick Gardner Behrends , Daniel Mark Nelson , Jeffrey Milton Scherer
发明人： Chad Allen Adams , Derick Gardner Behrends , Daniel Mark Nelson , Jeffrey Milton Scherer
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C11/41 , G11C29/1201
摘要： A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构和用于BIST（内置自检）的高性能SRAM（静态随机存取存储器）读取旁路的集成电路。该设计结构和集成结构包括用于SRAM阵列的读取输出的动态到静态转换单元和集成到动态到静态转换单元中的测试旁路单元，以便允许SRAM阵列的读取输出通过在不影响性能的非测试模式下，并绕过SRAM阵列的读取输出，并允许测试信号在测试模式下通过。

27. 发明授权

US07609542B2 Implementing enhanced SRAM read performance sort ring oscillator (PSRO) 有权
标题翻译：实现增强型SRAM读取性能排序环形振荡器（PSRO）
公开(公告)号：US07609542B2
公开(公告)日：2009-10-27
申请号：US11873534
申请日：2007-10-17
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/40
CPC分类号： G11C11/413
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：一种包括静态随机存取存储器（SRAM）单元的方法和装置实现增强的SRAM读取性能排序环形振荡器（PSRO），以及设置有被摄体电路所在的设计结构。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

28. 发明申请

US20080117695A1 DELAY MECHANISM FOR UNBALANCED READ/WRITE PATHS IN DOMINO SRAM ARRAYS 有权
标题翻译：多米诺SRAM阵列中不平衡读/写缓存的延迟机制
公开(公告)号：US20080117695A1
公开(公告)日：2008-05-22
申请号：US11560428
申请日：2006-11-16
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Derick Gardner Behrends , George Francis Paulik
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Derick Gardner Behrends , George Francis Paulik
IPC分类号： G11C7/00 , G11C8/10
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译：存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_wl和write_wl信号由字线解码器基于在下一周期中是执行读操作还是写操作生成。字线解码器包括具有用于接收write_wl信号的输入的缓冲器和用于输出write_wl信号的延迟版本的输出。基于read_wl信号和延迟的write_wl信号，字线信号由字线解码器激活。这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。

29. 发明授权

US07015600B2 Pulse generator circuit and semiconductor device including same 失效
标题翻译：脉冲发生器电路和包括它的半导体器件
公开(公告)号：US07015600B2
公开(公告)日：2006-03-21
申请号：US10268287
申请日：2002-10-10
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger
IPC分类号： H03K3/00 , H03K3/64 , G06F1/12
CPC分类号： H03K5/06 , H03K5/133
摘要： A pulse generator circuit is disclosed including a delay element coupled to a logic circuit. The delay element receives a clock signal CLK and a signal X and produces a signal XN dependent upon the clock signal CLK and the signal X. The logic circuit receives the clock signal CLK and the signal XN and produces a signal ACLK such that ACLK=CLK·XN′. The signal ACLK may include a series of positive pulses. The delay element may be, for example, one of multiple delay elements coupled in series, and signal X may be an output of a preceding one of the delay elements. A semiconductor device is described including the above pulse generator circuit and a self-resetting logic circuit. The self-resetting logic circuit receives the signal ACLK and one or more input signals and performs a logic operation using the one or more input signals during the positive pulses. The semiconductor device may include, for example, a random access memory (RAM) device, and the self-resetting logic circuit may form a part of a decoder circuit of the RAM device.
摘要翻译：公开了一种脉冲发生器电路，其包括耦合到逻辑电路的延迟元件。延迟元件接收时钟信号CLK和信号X，并产生取决于时钟信号CLK和信号X的信号XN。逻辑电路接收时钟信号CLK和信号XN，并产生信号ACLK，使得ACLK = CLK .XN'。信号ACLK可以包括一系列正脉冲。延迟元件可以是例如串联耦合的多个延迟元件中的一个，并且信号X可以是先前的一个延迟元件的输出。描述了包括上述脉冲发生器电路和自复位逻辑电路的半导体器件。自复位逻辑电路接收信号ACLK和一个或多个输入信号，并在正脉冲期间使用一个或多个输入信号执行逻辑运算。半导体器件可以包括例如随机存取存储器（RAM）器件，并且自复位逻辑电路可以形成RAM器件的解码器电路的一部分。

30. 发明申请

US20100188888A1 Implementing Enhanced Dual Mode SRAM Performance Screen Ring Oscillator 有权
标题翻译：实现增强型双模SRAM性能屏幕环形振荡器
公开(公告)号：US20100188888A1
公开(公告)日：2010-07-29
申请号：US12360230
申请日：2009-01-27
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C7/1045 , G11C8/18 , G11C11/412 , G11C11/413
摘要： A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.
摘要翻译：一种用于实现增强型双模式静态随机存取存储器（SRAM）性能屏幕环形振荡器（PSRO）的方法和电路，以及设置有被摄体电路的设计结构。双模SRAM PSRO包括连接在一起的多个SRAM基块。多个SRAM基块中的每一个包括八晶体管（8T）SRAM单元，局部评估电路和耦合到SRAM单元的逻辑功能。八晶体管（8T）静态随机存取存储器（SRAM）单元是未修改的8T SRAM单元。双模SRAM PSRO包括一种工作模式，其中输出频率由8T SRAM单元的直写性能决定; 和另一种操作模式，其中输出频率由8T SRAM单元的读取性能决定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式